【正文】 sum4 + 00110。amp。amp。 3．?dāng)?shù)據(jù)轉(zhuǎn)換模塊 ADC0809是8位模數(shù)轉(zhuǎn)換器，它的輸出狀態(tài)共有256種，若信號(hào)為0～5V電壓范圍，則每?jī)蓚€(gè)狀態(tài)的電壓差值為5/(2561)。139。139。 lock = 39。 oe = 39。 4 ale, start, oe, adda : OUT STD_LOGIC。OE=0，輸出數(shù)據(jù)線呈高阻態(tài)；OE=1，輸出轉(zhuǎn)換得到的數(shù)據(jù)。 分辨率是指A/D轉(zhuǎn)換器能分辨的最小模擬輸入量，通常用能轉(zhuǎn)換成的數(shù)字量的位數(shù)來表示，如8位、10位、12位、16位等。A/D Acquisition digital voltage一、緒 論研究目的及意義數(shù)字電壓表（Digital Voltmeter）簡(jiǎn)稱DVM，是大學(xué)物理教學(xué)和實(shí)驗(yàn)中的重要儀表，其數(shù)字化是指將連續(xù)的模擬電壓量轉(zhuǎn)換成不連續(xù)、離散的數(shù)字量并加以顯示。關(guān)鍵詞：電子設(shè)計(jì)自動(dòng)化(EDA)；FPGA；VHDL；A/D采集；數(shù)字電壓表AbstractThe design of digital system is being faster, bulkier ,smaller and lighter than before. Electronic design automation is in the last few years quickly develop, it makes use of software , hardware ,microelectronics technology to form a course of electronic design. Among them , the VHDL language of EDA is a kind of tool of fast circuit design , the function covered the circuit describe , the circuit synthesize , the circuit imitate the true etc . The circuit of the design that use VHDL language to plete . The this time design is primarily the applied software is MAX PLUS Ⅱ which is made by the United States ALTERA system’s range is 5v to +5v and precision is of this electric voltage watch is :Pass the software program to download the hardware o realize , design the period is short ,development the efficiency is high. Key words: Electronic Design Automation (EDA)。A/D轉(zhuǎn)換控制模塊控制外部A/D轉(zhuǎn)換器，動(dòng)態(tài)掃描與譯碼模塊向外部數(shù)碼管顯示電路輸出數(shù)據(jù)。 EOC——A/D轉(zhuǎn)換結(jié)束信號(hào)。 USE 。039。039。 lock = 39。 5 END PROCESS COM1。 對(duì)照波形仿真圖，我們看到dout端口的信號(hào)輸出均發(fā)生在st4狀態(tài)，仿真結(jié)果滿足時(shí)序要求，輸出結(jié)果正確，設(shè)計(jì)合理。 data0 =0000000000000000 WHEN datain(3 DOWNTO 0)=0000 ELSE 0000000000100000 WHEN datain(3 DOWNTO 0)=0001 ELSE 0000000000111001 WHEN datain(3 DOWNTO 0)=0010 ELSE 0000000001011001 WHEN datain(3 DOWNTO 0)=0011 ELSE 0000000001111000 WHEN datain(3 DOWNTO 0)=0100 ELSE 0000000010011000 WHEN datain(3 DOWNTO 0)=0101 ELSE 0000000100011000 WHEN datain(3 DOWNTO 0)=0110 ELSE 0000000100110111 WHEN datain(3 DOWNTO 0)=0111 ELSE 0000000101010111 WHEN datain(3 DOWNTO 0)=1000 ELSE 0000000101110110 WHEN datain(3 DOWNTO 0)=1001 ELSE 0000000110010110 WHEN datain(3 DOWNTO 0)=1010 ELSE 0000001000010110 WHEN datain(3 DOWNTO 0)=1011 ELSE 0000001000110101 WHEN datain(3 DOWNTO 0)=1100 ELSE 0000001001010101 WHEN datain(3 DOWNTO 0)=1101 ELSE 0000001001110101 WHEN datain(3 DOWNTO 0)=1110 ELSE 0000001010000100 WHEN datain(3 DOWNTO 0)=1111 ELSE 0000000000000000。 c2 = 00000 WHEN sum2 01010 ELSE 00001。 q1 = sum1(3 downto 0) WHEN sum1 01010 ELSE sum1 + 00110。 dpout : OUT STD_LOGIC。 END IF。 segout = b_sout。圖中賦予輸入信號(hào)din[7..0]=“01000110B”，設(shè)置時(shí)鐘信號(hào)和必要的控制信號(hào)，經(jīng)過仿真，輸出位選 1