【正文】 Entry – Compilation – Simulation – Timing Analysis – Device Programming ? Review and Support Copyright 169。 1997 Altera Corporation MAX+PLUS II Design Methodology Copyright 169。 check the design file with .gdf extension ? Correct any errors with the aid of Message Processor Design File Name Project Directory Copyright 169。 1997 Altera Corporation Design Entry Remendations ? Use LPM/Megafunction whenever possible ? Use hierarachical design methodology ? Use Hierarachy Display for fast access to design file at any level ? Use Message Processor to locate source of error in design file Copyright 169。 1997 Altera Corporation Controlling Logic Synthesis ? The logic synthesis operation is a tradeoff between area, speed, and easeoffit ? MAX+PLUS II gives users the control ? Two levels of controlling logic synthesis: – Individual logic level ? Localized effect ? Affects only the selected nodes, pins and logic blocks – Global logic level ? Global effect ? Affects all nodes, pins and logic blocks ? Remendation: use the logic synthesis controls only after design analysis of first pilation Copyright 169。 Route Making Global Project Device Options Assignment ? Choose Assign then Global Project Device Options ? Used to control device utilization – FLEX ? Reserve I/O pin and LCELL resources ? Select configuration method ? Assign dualuse configuration pins in FLEX devices ? Control devicewide reset and oe pins (FLEX 10K only) – Others ? Reserve I/O pin and LCELL resources ? Set security bit Copyright 169。 1997 Altera Corporation Design Files Simulation/ Timing Files Project Compilation Summary .gdf .tdf .vhd .sch .edf .xnf .snf MAX+PLUS II Compiler Compiler Netlist Extractor (includes all list readers Functional, Timing, or Linked SNF Extractor EDIF, VHDL amp。 1997 Altera Corporation Create Vector Simulation Stimulus ? Open Text Editor ? Type in vector stimulus – Clock – Pattern – Output % units default to ns % START 0 。 1997 Altera Corporation MAX+PLUS II Timing Simulation ? Used to debug timing related errors ? Advantages over Functional Simulation – Simulation of full synthesis result – Outputs change after timing delay ? Detection of oscillations, glitches and other timing related errors are possible ? Disadvantages – Longer pilation time – Combinatorial logic nodes cannot be simulated ? Node may be transformed or removed – Only “Hard” nodes can be simulated – Timing delays make debugging more difficult because cause and effect relationships are harder to locate Copyright 169。 1997 Altera Corporation Specify Length of Simulation ? Specify maximum length of simulation time with End Time Copyright 169。 1997 Altera Corporation Create Clock Waveform ? Snap to Grid On: Clock Period is twice the grid size ? Snap to Grid Off: Clock Period can be any value Hightlight waveform Clock shortcut Specify clock period Copyright 169。 1997 Altera Corporation BackAnnotation ? Lock “l(fā)ast successful pilation” into current assignments with BackAnnotate Project mand Copyright 169。 Pins field Drag and drop to make assignments to specific locations Nodes and pins can also be assigned to general areas like LAB, row or column Copyright 169。 1997 Altera Corporation Compiler Output Files ? Design verification files – MAX+PLUS II ? Simulation Netlist File (.snf) – 3rd Party EDA Tools ? VHDL list file (.vho) ? EDIF list file (.edo) ? Verilog list file (.vo) ? Standard Delay Format SDF file (.sdo) ? Programming files – Programmer Object file (.pof) – SRAM Object file (.sof) – JEDEC file (.jed) Copyright 169。 1997 Altera Corporation AHDL ? Altera Hardware Description Language ? Highlevel hardware behavior description language ? Uses Boolean equations, arithmetic operators, truth tables, conditional statements, etc. ? Especially wellsuited for large or plex state machines ? All described behavior is implemented concurrently ? Use Insert AHDL Template in the Text Editor Learn more about AHDL in the customer training class: Designing with MAX+plus II Using AHDL Copyright 169。 1997 Altera Corporation Making Connections ? Wire – Single bit line ? Bus – Multibit line ? Signal name – Matching name – Attached to wire Bus Bus signal names required for LPM module buses Wire Wire to Bus Connection Drawing tool shortcuts Copyright 169。 1997 Altera Corporation Or... ? Operate seamlessly with other EDA tools MAX+PLUS II Altera Gate Array Conversion Kit Verilog HDL amp。 1997 Altera Corporation MAX+PLUS II Can... ? Operate in a selfcontained environment Design Entry Design Compilation Verification amp。 1997 Altera Corporation Using LPM amp。 Check Option) Build the following circuit from the provided library VHDL Viewlogic EDIF AHDL LPM GDF Sel[1..0] Copyright 169。 Verilog Netlist Writers Database Builder Partitioner Design Doctor Logic Synthesizer Fitter Assembler 3rd Party EDA Design Files (.edf, .sch, .xnf) Functional SNF Files (.snf) Timing SNF Files (.snf) Programming Files (.pof, .sof, .jed) 3rd Party EDA Simulation/Timing Files (.edo, vo, vho, sdo) Mapping Files (.lmf) Assignments (.acf) Copyright 169。 1997 Altera Corporation From Floorplan Editor Making Pin/Location/Chip Assignment ? Select LAB View and Current Assignments Floorplan – must Save amp。 1997 Altera Corporation Floorplan Editor ? Graphical user interface for creating/viewing resource assignments – Pins – Logic cells – Cliques – Logic options ? Draganddrop capability for assigning pins/logic cells ? Graphical view of current assignments as well as last pilation results ? LAB view or external chip view Copyright 169。 Groups field Copyright 169。 Copyright 169。 1997 Altera Corpora