【正文】 ion needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1–Wire bus is in the inactive (high) state during the recovery period. If this does not occur and the bus is left low for more than 480 ms, all ponents on the bus will be reset. TRANSACTION SEQUENCE The protocol for accessing the DS1820 via the 1–Wire port is as follows: ? Initialization ? ROM Function Command ? Memory Function Command ? Transaction/Data INITIALIZATION All transactions on the 1–Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1820 is on the bus and is ready to operate. For more details, see the “1–Wire Signaling” section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the five ROM function mands. All ROM function mands are 8–bits long. A list of these mands follows (refer to flowchart in Figure 6): Read ROM [33h] This mand allows the bus master to read the DS1820’s 8–bit family code, unique 48–bit serial number,and 8–bit CRC. This mand can only be used if there is a single DS1820 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired AND result). Match ROM [55h] The match ROM mand, followed by a 64–bit ROM sequence, allows the bus master to address a specific DS1820 on a multidrop bus. Only the DS1820 that exactly matches the 64–bit ROM sequence will respond to the following memory function mand. All slaves that do not match the 64–bit ROM sequence will wait for a reset pulse. This mand can be used with a single or multiple devices on the bus. Skip ROM [CCh] This mand can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64–bit ROM code. If more than one slave is present on the bus and a read mand is issued following the Skip ROM mand, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired AND result). Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1–Wire bus or their 64–bit ROM codes. The search ROM mand allows the bus master to use a process of elimination to identify the 64–bit ROM codes of all slave devices on the bus. 英文資料譯文 DS1820 特性： 與 DS1820 的通信經(jīng)過一個(gè)單線接口。第一種方法是發(fā)生溫度變換時(shí)，在 I/O 線上提供一強(qiáng)的上拉。 DS1820 通過門開通期間內(nèi)低溫度系數(shù)振蕩器經(jīng)歷的時(shí)鐘周期個(gè)數(shù)計(jì)數(shù)來測量溫度，如果在門開通期結(jié)束前計(jì)數(shù)器達(dá)到零，那么溫度寄存器 — 它也被予置到 55℃ 的數(shù)值 — 將增量，指示溫度高于 55℃。這個(gè)值便是 TEMP_READ。存貯器操作命令 如果在總線上存在多于一個(gè)的從屬器件而且在 Skip ROM 命令之后發(fā)出讀命令，那么由于多個(gè)從片同時(shí)發(fā)送數(shù)據(jù)，會在總線上發(fā)生數(shù)據(jù)沖突（漏極開路下拉會產(chǎn)生“線與”的效果）。 Match ROM(“ 符合” ROM) [55h] “符合” ROM 命令。如果不滿足這一點(diǎn)且總線保持在低電平時(shí)間大于 480us， 那么總線上所有器件均被復(fù)位。數(shù)據(jù)在單線接口上串行發(fā)送。在此命令發(fā)出后，主機(jī)接著發(fā)出讀時(shí)間片。當(dāng) I/O或 VDD 引腳為高電平時(shí)，這個(gè)電路便“取”得電源。用戶可定義的，非易失性的溫度告警設(shè)置； C resolution. The temperature reading is provided in a 16–bit, sign–extended two’s plement reading. Table 1 describes the exact relationship of output data to measured temperature. The data is transmitted serially over the 1–Wire interface. The DS1820 can measure temperature over the range of –55176。C increments. Fahrenheit equivalent is –67176。獨(dú)特的單線接口，只需 1 個(gè)接口引腳即可通信； 在單線接口情況下，在 ROM 操作未定建立之前不能使用存貯器和控制操作。如圖 2所示，通過使用