【正文】 ction for the ICL7106 and ICL7107, respectively. In the ICL7106, an internal digital ground is generated from a 6V Zener diode and a large PChannel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. Figure 6 is the Digital Section of the ICL7107. It is identical to the ICL7106 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size mon anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. In both devices, the polarity indication is “on” for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired.FIGURE 5 ICL7106 DIGITAL SECTIONFIGURE 6 ICL7107 DIGITAL SECTION System TimingFigure 7 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements can be used:1. Figure 7A. An external oscillator connected to pin 40.2. Figure 7B. An RC oscillator using all three pins.The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convertcycle phases. These are signal integrate (1000 counts), reference deintegrate (0 to 2000 counts) and autozero (1000 to 3000 counts). For signals less than full scale, autozero gets the unused portion of reference deintegrate. This makes a plete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 33kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 66kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz ( readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz).FIGURE 7 CLOCK CIRCUITS三位半LCD/LED顯示A/D轉(zhuǎn)換器摘要：ICL7106和ICL7107是高性能、低功耗的三位半A/D轉(zhuǎn)換電路。(2)1pA典型輸入電流。每個測量周期分為三個階段，他們分別是（1）自動校零階段（A~Z）；（2）信號積分階段（INT）和（3）反向積分階段（DE）。轉(zhuǎn)換器將IN HI和IN LO之間輸入的差動輸入電壓進行一固定時間的積分，此差動輸入電壓可以在一個很寬的共模范圍內(nèi)，與正、負電源的差距各為1V之內(nèi)。在此范圍內(nèi)，電路有85dB的共模抑制比。 模擬公共端此管腳主要是為在電池供電的應(yīng)用場合（ICL7106）或輸入信號相對于供電電源是浮動的系統(tǒng)中建立一個公共電壓而設(shè)置的。參考源有正溫度系數(shù)的電路在量程溢出時會多出幾個字。如果IN LO不同于模擬公共端，就會在系統(tǒng)中產(chǎn)生一共模電壓并會被電路優(yōu)異的共模抑制特性所抑制，然而在某些應(yīng)用場合，IN LO會被設(shè)置成一已知的固定電壓（比如電源的公共端），這樣，模擬公共端也應(yīng)該至此同一點，以消除電路上的共模電壓。在ICL7106電路中，它通過—500Ω的電阻連接到內(nèi)部產(chǎn)生的數(shù)字部分電源。標(biāo)稱電壓幅度為5V；LCD的端驅(qū)動電壓與此背極電壓同頻、同幅，不顯示時為同相，顯示時為反相，在各種條件下，字符段兩端的平均直流電壓可以忽略。（2）如圖7B中所示，用三個管腳構(gòu)成R