sci(uart)(完整版)
【正文】 eUP TCIE Transmit Complete Interrupt Enable 1 = Transmitter Complete IRQ Enabled 0 = Transmitter Complete IRQ Disabled RIE Receiver Interrupt Enable 1 = Receiver IRQ Enabled 0 = Receiver IRQ Disabled TIE Transmitter Interrupt Enable 1 = Transmitter IRQ Enabled 0 = Transmitter IRQ Disabled SCI Registers 3/5 Lecture4 Page 38 微控制器開發(fā)技術(shù) SCISR 1 SCI Status Register 1見 XS128芯片手冊 P409 SCI Registers 4/5 SCISR 2 SCI Status Register 2見 XS128芯片手冊 P410 RAF Receiver Active Status 1 = Receiver Active 0 = Receiver not Active BRK13 Break Transmit Character Length 0 = Break Char is 10 or 11 bits long 1 = Break Char is 13 or 14 bit long TXDIR Transmitter pin direction 0 = TxD pin is input in SingleWire mode 1 = TxD pin is output in SingleWire mode RDRF: Receive data Register Full TC : Transmit Complete TDRE: Transmit data register empty Lecture4 Page 39 微控制器開發(fā)技術(shù) SCIDRH/L SCI Data Register High/Low Note: R8 and T8 are used when 9bit char is required SCI Registers 5/5 Notice: same register for both transmit data and receive data Lecture4 Page 40 微控制器開發(fā)技術(shù) SCI programming Put_Char BRCLR SCI0SR1,$80,* STAB SCI0DRL RTS void Put_Char(char c) { while ( (SCI0SR1 0x80) == 0)。 ?數(shù)據(jù)位傳送之前，都要發(fā)送 START 位(always ‘ 0’ ) (從空閑狀態(tài)開始的下降沿，是 START位的開始） ?在數(shù)據(jù)位傳送結(jié)束后，還要傳送 STOP位 (always ‘ 1’ ). Lecture4 Page 20 微控制器開發(fā)技術(shù) 數(shù)據(jù)位識別 ?接受端在其時鐘上升沿采樣數(shù)據(jù)線電平，以識別數(shù)據(jù)位的高低狀態(tài)。 { while ((SCI0SR1 0x20) == 0)。16 Shift register Parity gen Control logic Interrupt request gen Lecture4 Page 33 微控制器開發(fā)技術(shù) Receiver block diagram Rx data register shift register Rx clock gen Control logic Lecture4 Page 34 微控制器開發(fā)技術(shù) SCI(UART)見 XS128P399 Lecture4 Page 35 微控制器開發(fā)技術(shù) SCIBH/L SCI Baud Rate Control Register見 XS128芯片手冊 P402 必須連續(xù)寫入 BDH和 BDL寄存器，僅僅寫入 BDH沒有作用。 Lecture4 Page 21 微控制器開發(fā)技術(shù) 數(shù)據(jù)位識別 Tx_clk Rx_clk TxD RxD 傳輸過程會引起信號的延遲，會引入外部干擾導(dǎo)致的噪聲及毛刺 Lecture4 Page 22 微控制器開發(fā)技術(shù) SCI(UART)oversampling 通信雙方有約定的通信速率（波特率） 接受端按照 16倍波特率的頻率對信號進(jìn)行 over samples 使用其中 3個采樣結(jié)果，通過 3取 2的機制確定實際的信號電平狀態(tài) 如果 3個采樣結(jié)果不一致， noise標(biāo)志會置起 接收
環(huán)評公示相關(guān)推薦
鄂ICP備17016276號-1