esdprotectiondesignseminar英文版(完整版)
【正文】 ancesAlso put protection diodes at most likely ESD entry point the connectorPreferred LayoutESD EntryPointParasitic LVccGndProtectedDevicePoor layout increased clamp voltagedue to parasitic inductanceParasitic LVccGndProtectedDeviceESD EntryPoint2023/3/4 18Designing for Minimal PowerRail Inductance2023/3/4 19Add Bypass Capacitor Place Ceramic bypass capacitor ( ~ uF) as close as possible to ESD diode work power rail to shunt ESD current to both power rails Maybe add Zener in parallel with capacitor to minimize parasitic inductance of bypass capacitorProtectedDeviceGndVccC2023/3/4 20Using a Series Resistor toMinimize Downstream Current4 Can be considered for latchup sensitive applications4 Guaranteed clamping voltage limits current downstream (I = V / R)4 Only for inputs with high Z4 Only for output drivers with low Z watch out for filtering of signal2023/3/4 21Powerdown Issues4 Diode protected systems that are powered down can drain current from an active high input through the diode to VCC 4 This can drain batteries and/or damage devices on the same line4 To avoid this, isolate VCC from the bypass capacitor with a blocking diode4 One diode solution2023/3/
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