【正文】 at the highest speed when Ncap is 1 and the lowest speed when Ncap is 0xffff. Table 12 Motor Speed VS Clock Frequency Fcap n FCK/1 FCK/4 FCK/16 FCK/64 FCK/256 FCK/1024 Nmax (rpm) 120M 30M 1875K 468750 Nmin (rpm) 1831 ＠ When m= 3, TCNT is cleared for once every 3 times P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared every 180 electrical degree rotation of BLDC. From the Formula 1 4, we can see that the measurable motor speed when m= 3 is three times higher than that when m= 1, provided that other parameters are the same. ＠ When m= 6, TCNT is cleared every 6 times P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared every 360 electrical degree rotation of BLDC. From the Formula 1 4, we can see that the measurable motor speed when m= 6 is six times higher than that when m= 1, provides that other parameters are the same. Above all, it is better to set m= 1 to ensure the veracity of positions. Since the highest speed can be applied, it is important to select the lowest speed. Assume the lowest measure speed is 200 rpm, we can set Fcap as FCK/16, FCK/64, FCK/256 or FCK/1024. FCK/16 is remended to be selected for higher veracity. Noise Immunity 10 Through programming the bit value of SPLCNT (sampling count select) and SPDLY (sampling delay) in P_POSx_DectCtrl(x = 0, 1), users could avoid the erroneous detection due to noise that occurs immediately after PWM output turns on. It can ensure the correctness of speed measurement and phase mutation in BLDC . The valid settings are from 1 to 15 times. Note that count 0 and 1 are both assumed to be one time. These bits select the sampling count for the valid external position detection signals. The position signals must be sampled continuously match as many times as the sampling count set, for the position signals to be considered valid. Then the sharp pulse can be filtered by this method. SPLCK selects the sampling clock. Figure 12 shows the sampling counting and Figure 13 shows the noise immunity pulse. Figure 12 Sampling Counting Figure 13 Noise Immunity Pulse See Figure 12 , the SPLCNT setting is 10. When sampling the position signal with the frequency that SPLCK selected, a hightolow transition occurs in hall3 at 0 to1 counting. Then sample the hall signal for ten executive times. If they are all of the same 0 1 2 3 4 5 6 7 8 9 10 Hall3 Hall2 Hall1 SPLCK … Hall3 Hall2 Hall1 …… … 0 1 2 3 4 5 6 11 value, the hall signal can be considered valid. When SPLCNT setting is 10, a hightolow transition occurs in hall3 at the first counting, while a lowtohigh transition occurs at the fourth counting. Then reset the counter, sample hall3 for ten executive times. If they are all of the same value, the position signals can be considered as 011b still. By this way, a sharp pulse occurring in the signals can be filtered, which prevents the position signals from being disturbed. So the position signal will not be sampled if it varies quicker than the setting of SPLCK/SPLCNT does (note that count 0 and 1 are assumed to be one time). 2 Software Design Software Description This application note is designed for motor speed measurement when driving BLDC, which is performed by PDC position detection change interrupt. Source File File Name Function Type Main System initialization and motor detection (or performed by ISR) C ISR Position detection change input and speed calculation C Spmc75 _SPDET_V100 The key function for speed calculation lib DMC munication function lib DMC Interface Speed1_Now: Current speed by calculation User_R0: PDC Data captured by PDC interrupt Subroutines Spmc75_System_Init ( ) Prototype void Spmc75_System_Init(void) Description Initialize PDC Timers and DMC Input Arguments None Output Arguments None 12 Head Files Library Files Spmc75_ SPDET _V100 Note PDC timer0 is initialized here Example Spmc75_System_Init()。 // Counting at rising edge P_TMR0_Ctrl, = 3。 // Select FCK/64 clock source Position Detection Control Register P_POSx_DectCtrl(x = 0, 1) B15 B14 B13 B12 B11 B10 B9 B8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SPLCK SPLMOD SPLCNT B7 B6 B5 B4 B3 B2 B1 B0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 PDEN SPDLY Bit 15:14 SPLCK: Sampling clock select. Select FCK/4, FCK/8, FCK/32, or FCK/128 for position sampling clock 00 = FCK/4 01 = FCK/8 7 10 = FCK/32 11 = FCK/128 Bit 13:12 SPLMOD: Sampling mode select. Select one of three modes: sampling when PWM signal is active (PWM is on), sampling regularly, or sampling when lower side (UN, VN, WN) phases are conducting current. 00 = Sample when UPWM/VPWM/WPWM bit is set in P_TMRx_OutputCtrl (x = 3, 4) register and generate the PWM waveform 01 = Sample regularly 10 = Sample when lower phases is in active state and conducting current 11 = Reserved Bit 11:8 SPLCNT: Sampling count select. These bits select the sampling count for the valid external position detection signals. The position signals must be sampled continuously match as many times as the sampling count set, for the position signals to be considered valid. The valid settings are from 1 to 15 times. Note that count 0 and 1 are assumed to be one time. Bit : 7 PDEN: Position detection enable. This bit enables/disables the position detection function for position input pins TIOA~C. When enabled, the input signals of these pins will be sampled and the results will be latched to PD