【正文】 eriodSlack = Slack clock period – (Micro tCO+ Data Delay + Micro tSU)Clock SkewClock Skew指一個同源時鐘到達兩個不同的寄存器時鐘端的時間偏移。它與Xilinx的時序定義中，有一個概念叫Tcko是同一個概念。Clock Setup Time (tsu)要想正確采樣數(shù)據(jù)，就必須使數(shù)據(jù)和使能信號在有效時鐘沿到達前就準備好，所謂時鐘建立時間就是指時鐘到達前，數(shù)據(jù)和使能已經(jīng)準備好的最小時間間隔。 BEFORE CLK約束，也可以直接對芯片內部的輸出邏輯直接進行約束，NET DATA_OUT OFFET=OUTAFTER CLK約束，也可以使用OFFSET_IN_BEFORE對芯片內部的輸入邏輯進行約束，其語法如下：NET DATA_IN OFFET=INXilinx把上述約束統(tǒng)稱為：OFFSET約束（偏移約束），一共有4個相關約束屬性：OFFSET_IN_BEFORE、OFFSET_IN_AFTER、OFFSET_OUT_BEFORE和OFFSET_OUT_AFTER。其中TOUTPUT為設計中連接同步元件輸出端的組合邏輯、網(wǎng)線和PAD的延遲之和，TCKO為同步元件時鐘輸出時間。 公式2將公式1代入公式2：Tarrival+Tinput+TsetupTclk_skew=Tclk, 而Tclk_skew滿足時序關系后為負，所以TARRIVAL +TINPUT+TSETUP TCLK關于輸入到達時間，這一貼估計問題比較多，看起來也比較累，但是沒有辦法，這些都是時序的基本概念啊。時鐘的最小周期為：TCLK = TCKO +TLOGIC +TNET +TSETUP －TCLK_SKEWTCLK_SKEW =TCD2 －TCD1其中TCKO為時鐘輸出時間，TLOGIC為同步元件之間的組合邏輯延遲，TNET為網(wǎng)線延遲，TSETUP為同步元件的建立時間，TCLK_SKEW為時鐘信號延遲的差別。例如用OFFSET_IN_BEFORE約束可以告訴綜合布線工具輸入信號在時鐘之前什么時候準備好，綜合布線工具就可以根據(jù)這個約束調整與IPAD相連的Logic Circuitry的綜合實現(xiàn)過程，使結果滿足FFS的建立時間要求。靜態(tài)時序分析工具以約束作為判斷時序是否滿足設計要求的標準，因此要求設計者正確輸入約束，以便靜態(tài)時序分析工具輸出正確的時序分析報告。 多謝mentor老師。 t reducing the frequency to settle the hold violation as setup violation ?could you explain it clearer ?Equation for Setup TimeTclk Tclktoq + Tlogic + Tsetup + Tskew + TjitterEquation for Hold TimeTclktoq + Tlogic Tskew TholdNote that Hold Time equation is independent of clk frequency( Time period Tclk)key things to note from above equationsa) once the silicon es back , if u have setup time problem , u canincrease the clock period (Tclk) to fix it , whereas if u have holdtime problem , its a more serious problem and u will need a newmetal fix tapeout . ( But u can still test the current chip using Low supply voltage,or High temperature or SS corner part that decrease hold time violation) Hi koggestone, It is nice information. Could you please give us more information on u will need a new metal fix tapeout . ( But u can still test the current chip using Low supply voltage, or High temperature or SS corner part that decrease hold time violation)what i meant was , when u have hold time violation , u dont need to throw away chip and wait for 3 months for fixed chip to e back. in the meanwhile , by playing with voltage and temperature , u can do other functional tests on the chip . since normally hold time simulation are done at FF corner , high voltage, low temperature which is the pessimistic case for hold time , by decreasing voltage , using high temperature, and a SS corner chip , we may be lucky enough to find a part that works , to do other functional tests to catch any other bugs before next tapeout.下面這個比較詳細：Sunil Budumuru：Pls. make a note that HOLD violations are dangerous than SETUP. To keep it simple way, SETUP timing depends on the frequency of operation. But HOLD time is not. Let us see the equations here. T = Frequency of operation (can be variable) Tcq = Flop clock to Flop output delay (fixed/constant) Tb = Delay od the binational logic between the Flops (can be variable) Tsetup = Setup time of a Flop (fixed/constant) Thold = Hold time of a Flop (fixed/constant) Tskew = Delay between clock edges of two adjacent flops (delay offered by clock path) (can be variable) For SETUP, T = Tcq + Tb + Tsetup Tskew If you have setup time means u r violating the above rule. some how the equation bees T Tcq + Tb + Tsetup Tskew Now let us consider two cases. Case1: During the Design development phase itself. Now, you have three variables (T, Tb, Tskew.) to avoid the setup violation. T : Reduce the frequency such that u saticify T = Tcq + Tb + Tsetup Tskew. But do u think it is the correct solution. Obviously, NO. This is because we have other options to avoid setup violations right. Tb : If you reduce the binational delay (between the Flops of violated path) such a way that T Tcq + Tb + Tsetup Tskew will bee T = Tcq + Tb + Tsetup Tskew. So, the SETUP violation is avoided. How do u reduce the binational delay??? Try different logic structure without effecting the functionality. or try to reduce the more fanout nets within the logic. Or upsize or downsize the cells. If it worked out thats fine. Tskew: If u increase the skew, u can change T Tcq + Tb + Tsetup Tskew to T = Tcq + Tb + Tsetup Tskew. How to increase the Tskew? Just keep buffers in the clock path. But be sure doesnt effect the HOLD timing. Case2: After the CHIP is manufatured and is in your hand. In this case, one cannot access the Tb and Tskew. Only the variable that can handle is T. So, Just reduce the frequency (T) such that the violated equation, T Tcq + Tb + Tsetup Tskew bees violation free equation T = Tcq + Tb + Tsetup Tskew. So, if u have setup violations on a manufatured chip, u can make it work by reducing the frequency. For HOLD, Thold + Tskew = Tcq + Tb If you have setup time means u r violating the above rule. some how the equation bees Thold + Tskew Tcq + Tb and ur aim is to make Thold + Tskew = Tcq + Tb Now let us consider two cases. Case1: During the Design development phase itself. You have two variables in hand (Tb, Tskew) to avoid HOLD violations. Tb: Increase the Tb by adding buffers in the data path. Thus u can change the situation from Thold + Tskew Tcq + Tb to Thold + Tskew = Tcq + Tb. But thi