【正文】 pares the number of tracks required to place and pletely route circuits with VPR with the number required to place and globally route the circuits with VPR and then perform detailed routing with SEGA [23]. Table 5 also gives the size of each circuit， in terms of the number of logic blocks. The entries in the SEGA column with a 179。 Dlimit 163。此外，我們已經提出更大的電路基準測試結果。由 VPR增加路由產生的全版圖航線曲目總數(shù)，有超過所需 68％路線的電路主場由 VPR路由完全執(zhí)行。因此在本節(jié)中我們目前的實驗結果， 20個最大的 MCNC基準電路 [27]，它的大小范圍從 1047到 8383邏輯塊。 VPR使用少于 13％資源數(shù)目的同時，它將執(zhí)行合并后的全球和詳細的路由，世嘉比用于執(zhí)行詳細路由對 AA VPR生成全版圖走線。作為商業(yè)化的 FPGA，實現(xiàn)從一個輸入引腳接線盒到多路通道，只有一個軌道可以連接到輸入引腳，使用多路復用器而不是獨立通過在 FPGA中的晶體管布局來保存相當?shù)拿娣e。所得結果在本節(jié)獲得了邏輯的 4輸入 LUT加上一個觸發(fā)器組成的塊，如圖所示在圖 2。高扇出網(wǎng)絡通?？缭酱蟛糠?或所有的 FPGA。為了避免過于迂回路線以節(jié)省 CPU時間，我們讓一個去凈路由最外的 3 個通道的凈終端 邊界框。該運動的邏輯塊總是至少影響到一個網(wǎng)。有了這個動機，我們提出了一個新的溫度更新附表，在溫度增加的時間花費在一個重要的小區(qū)域上，但不是全部動作都被接受。我們首先創(chuàng)建一個隨機安置的電路。 Q是對總體 1有 3個或更少的終端，并慢慢增加了 50臺網(wǎng)邏輯與上 。 VPACK也針對邏輯塊包含幾個有用的 LUT和幾個拖動程序，有或沒有共享 LUT的輸入 [6]。添加新的路由架構的功能 VPR相對容易，因為 VPR使用體系結構描述來創(chuàng)建路由資源圖。 2 2 概述 VPR 圖 1 概括了 VPR 的 CAD 流程。本文介紹了通用的地點和路線（ VPR）工具，設計很靈活，足夠讓許多 FPGA架構的比較 VPR可以執(zhí)行的位置，要么全球路由或合并后的全球詳細路由。在減少路由面積計算方面， VPR優(yōu)于所有的 FPGA布局布線工具，我們可以比較。 1 簡介 在 FPGA 的研究中，人們通常必須評估新結構特色的實用工具而做評估實驗。在第 3和第 4節(jié)，我們描述了布局布線法。此外，如果全球路由要執(zhí)行，你也可以指定： ?橫向和縱向通道的相對寬 度之和 ?在不同區(qū)域的 FPGA的渠道相對寬度。最后， VPR的內置圖形允許交互式可視化的布局，路由可用資源和互連的可能途徑路由資源。對于每一個網(wǎng)，北方新宇和 bby指出在其邊界框的水平和垂直跨度分別為 Q（ n）的因數(shù)補償。我們已經開發(fā)出一種新的退火附表，導致非常高品質的展示位置，并在其中給出退火參數(shù)的自動調節(jié)功能，不同的成本和電路尺寸。減少溫度每秒移動數(shù)的 10倍，例如，加快安置到 10倍，并降低了大約只有 10％的最終填筑質量。而這些 “本地交換 “往往導致安置成本相對較小的變 化，越來越多被接受的可能性增加。對使用路由資源成本的函數(shù)，其對資源的任何過度使用都會讓當前路由發(fā)生事先迭代。波前的迷宮路由被清空，新波前擴展是從整個網(wǎng)絡布線開始發(fā)出的。由于增加新的路徑路由的部分有一個零成本，由于這項新路徑通常相當小迷宮路由器將首先擴大它范圍，也需要相對較少的時間來添加此新波，如果整個波前擴展了能實現(xiàn)那么下一個接收器 6 將達到的速度遠遠超過現(xiàn)在。 Doglegs 以往大多數(shù) FPGA布線結果認為 “輸入引腳 doglegs”是可能。列出三兩步（全球和詳細）路由與其它路由器進行合并后的全球和詳細的路由。當然這些工具都支持允許布局和布線的電路，對于 SPLACE / SROUTE組合 VPR還需要少 29％資源數(shù)目。表 5還給出了大小每個邏輯塊的數(shù)量計算電路。而不是 1美元），由他們來處理如果減少需要跟蹤的總數(shù)。在不久的將來 VPR將支持緩沖和分段路由結構，我們計劃增加定時分析儀和時序驅動的路由。 sign could not be successfully routed because SEGA ran out of SEGA to perform detailed routing on a global route generated by VPR increases the total number of tracks required to route the circuits by over 68% vs. having VPR perform the routing pletely. Clearly SEGA has difficulty routing large circuits when input pin doglegs are not encourage other FPGA researchers to publish routing results using these larger benchmarks， we issue the following “FPGA challenge.” Each time verified results which beat the previously best verified results on these benchmarks are announced， we will pay the authors $1 (sorry， $1 Cdn.， not $1 .) for each track by which they reduce the total number of tracks required from that of the previously best results. The 20 technologymapped lists， the placements generated by VPR and the currently best routing track total are available at 6 Conclusions and Future Work We have presented a new FPGA placement and routing tool that outperforms all such tools to which we can make direct parisons. In addition we have presented benchmark results on much larger circuits than have typically been used to characterize academic FPGA place and route tools. We hope the next generation of FPGA CAD tools will be pared on the basis of these larger benchmarks， as they are a closer approximation of the kind of problems being mapped into today’s of the main design goals for VPR was to keep the tool flexible enough to allow its use in many FPGA architectural studies. We are currently working on several improvements to VPR to further increase its utility in FPGA architecture research. In the near future VPR will support buffered and segmented routing structures， and soon after that we plan to add a timing analyzer and timingdriven routing. 21 References [1] S. Brown， R. Francis， J. Rose， and Z. Vranesic， FieldProgrammable Gate Arrays， Kluwer Academic Publishers， 1992. [2] Xilinx Inc.， The Programmable Logic Data Book， 1994. [3] AT amp。 q is 1 for s with 3 or fewer terminals， and slowly increases to for s with 50 ， x(n) and Cav， y(n) are the average channel capacities (in tracks) in the x and y directions， respectively， over the bounding box of cost function penalizes placements which require more routing in areas of the FPGA that have narrower channels. All the results in this paper， however， are obtained with FPGAs in which all channels have the same capacity. In this case Cav is a constant and the linear congestion cost function reduces to a bounding box cost good annealing schedule is essential to obtain highquality solutions in a reasonable putation time with simulated annealing. We have developed a new annealing schedule which leads to very highquality placements， and in which the annealing parameters automatically adjust to different cost functions and circuit sizes. We pute the initial temperature in a manner similar to [11]. Let Nblocks be the total number of logic blocks plus the number of I/O pads in a circuit. We first create a random placement of the circuit. Next we perform Nblocks moves (pairwise swaps) of logic blocks or I/O pads， and pute the standard deviation of the cost of these Nblocks different configurations. The initial temperature is set to 20 times this standard deviation， ensuring that initially virtually any move is accepted at the start of the in [12]， the default number of moves evaluated at each temperature is. This default number can be overridden on the mand line， however， to allow different CPU time / placement quality tradeoffs. Reducing the number of moves per temperature by a factor of 10， for example， speeds up placement by a factor of 10 and reduces final placement quality by only about 10%.When the temperature is so high that almost any move is accepted， we are essentially moving randomly from one placement to ano