【正文】 s is ? User can customize own styles Copyright 169。 pins are listed in the Unassigned Nodes amp。 1997 Altera Corporation The Timing Compilation Process ? Compiler Netlist Extractor and Database Builder build list database and check for syntax errors ? Logic Synthesizer performs logic synthesis/minimization ? Design Doctor checks for design violations ? Partitioner and Fitter executes place amp。 1997 Altera Corporation Floorplan Editor ? Last Compilation Floorplan Device View Pin number Pin name Color Legend definition Copyright 169。 1997 Altera Corporation MAX+PLUS II Simulator MAX+PLUS II Waveform Editor .scf .snf MAX+PLUS II Text Editor MAX+PLUS II Simulator MAX+PLUS II Compiler .scf .vec MAX+PLUS II Waveform Editor Copyright 169。 1997 Altera Corporation Draw Stimulus Waveform ? Highlight portion of waveform to change ? Overwrite with desired value (Group value or single bit) Hightlight waveform Overwrite value Overwrite shortcut Copyright 169。 INPUTS CLOCK 。 1997 Altera Corporation Select Simulation Stimulus File ? Defaults to .scf file ? For vector input stimulus, set Vector Files Input to .vec file Set to .vec file Copyright 169。 1997 Altera Corporation Demo 1 Demo the Waveform Editor Copyright 169。 1997 Altera Corporation ? Open first channel file ? Choose Compare under File menu ? Select the name of the second channel file with the Compare dialog box ? Deviations of second channel file from the first are highlighted Compare Two Simulation Files Comparing Different Simulations Copyright 169。 Copyright 169。 STOP 1000 。 Groups field Copyright 169。 Verilog Netlist Writers Database Builder Partitioner Design Doctor Logic Synthesizer Fitter Assembler .edo .vo .vho 3rd Party EDA Files Programming Files .pof Report Files .rpt .sdo Copyright 169。 1997 Altera Corporation Floorplan Editor ? Graphical user interface for creating/viewing resource assignments – Pins – Logic cells – Cliques – Logic options ? Draganddrop capability for assigning pins/logic cells ? Graphical view of current assignments as well as last pilation results ? LAB view or external chip view Copyright 169。 1997 Altera Corporation Compiler Processing Options ? Functional – Compilation generates file for Functional Simulation ? Functional SNF file (.snf) ? Timing – Compilation generates user selectable files for ? Timing Simulation and Timing Analysis – Timing SNF file (.snf) ? 3rd party EDA Simulation – Verilog file (.vo) – VHDL file (.vho) – SDF file (.sdo) ? Device Programming – Altera Programmer file (. .pof, .sof) Copyright 169。 1997 Altera Corporation From Floorplan Editor Making Pin/Location/Chip Assignment ? Select LAB View and Current Assignments Floorplan – must Save amp。 1997 Altera Corporation Individual Logic Level Control ? Highlight node, pin or logic block ? Choose Assign menu then Logic Options ? Two ways of making individual logic level assignment: – Individual Logic Options assignment – Synthesis Styles assignment Copyright 169。 Verilog Netlist Writers Database Builder Partitioner Design Doctor Logic Synthesizer Fitter Assembler 3rd Party EDA Design Files (.edf, .sch, .xnf) Functional SNF Files (.snf) Timing SNF Files (.snf) Programming Files (.pof, .sof, .jed) 3rd Party EDA Simulation/Timing Files (.edo, vo, vho, sdo) Mapping Files (.lmf) Assignments (.acf) Copyright 169。 1997 Altera Corporation Design Files Support Files Design Entry Summary MAX+PLUS II Graphic Editor MAX+PLUS II Text Editor MAX+PLUS II Symbol Editor MAX+PLUS II Waveform Editor .gdf .tdf .vhd .sch .edf .xnf MAX+PLUS II 3rd Party EDA Tools .sym .inc User .wdf .lmf Copyright 169。 Check Option) Build the following circuit from the provided library VHDL Viewlogic EDIF AHDL LPM GDF Sel[1..0] Copyright 169。 1997 Altera Corporation Message Processor ? Lists all Info, Warning and Error messages – Info messages are general information – Warning messages are possible problems – Error messages indicate Compiler is unable to plete pilation process ? Provides help on the messages ? Locates source of message in design file Messages Go to next or previous message Information about message Locate source in design file Copyright 169。 1997 Altera Corporation Using LPM amp。 1997 Altera Corporation System Production Design Specification Design Compilation Functional Verification Timing Verification Device Programming InSystem Verification Design Modification Design Entry Copyright 169。 1997 Altera Corporation MAX+PLUS II Can... ? Operate in a selfcontained environment Design Entry Design Compilation Verification amp。 1997 Altera Corporation Designing with MAX+PLUS II Copyright 169。 1997 Altera Corporation Or... ? Operate seamlessly with other EDA tools MAX+PLUS II Altera Gate Array Conversion Kit Verilog HDL amp。 1997 Altera Corporation ? Set up a new project ? Draw schematic – Enter symbols – Connect wires – Type in signal names ? Save and check the design – The file extension is .gdf – Correct any errors with the aid of Message Processor ? Create symbol or include file Graphic Design Entry Copyright 169。 1997 Altera Corporation Making Connections ? Wire – Single bit line ? Bus – Multibit line ? Signal name – Matching name – Attached to wire Bus Bus signal names required for LPM module buses Wire Wire to Bus Connection Drawing tool shortcuts Copyright 169。 1997 Altera Corporation Example Section (LAB 1) Copyright 169。 1997 Altera Corporation AHDL ? Altera Hardware Description Language ? Highlevel hardware behavior description language ? Uses Boolean equations, arithmetic operators, truth tables, conditional statem