【正文】 1997 Altera Corporation Example Section (LAB 3) Copyright 169。 1997 Altera Corporation Save the Vector Stimulus File ? Save the vector stimulus file with .vec extension – You must change the .vec extension since MAX+PLUS II defaults to .tdf extension for text files Change the extension to .vec Copyright 169。 INTERVAL 100 。 1997 Altera Corporation Grid Control ? Snap to Grid – On: waveforms drawn increments of grid size – Off: waveforms can be drawn to any size Set Grid size Copyright 169。 1997 Altera Corporation System Production Design Specification Design Entry Project Compilation Device Programming InSystem Verification Design Modification Simulation Timing Analysis Copyright 169。 1997 Altera Corporation Floorplan Editor ? Last Compilation Floorplan Full Screen LAB View with Report File Equation Viewer Fanin and Fanout Highlighted LCELL LCELL equation Display control Copyright 169。 1997 Altera Corporation The Functional Compilation Process ? Compiler Netlist Extractor builds the .f list file and checks for syntax errors ? Database Builder constructs the node name database ? Functional SNF Extractor build .snf file for functional simulation Copyright 169。 Check the project first All nodes amp。 1997 Altera Corporation Individual Logic Option Assignment ? Provides controls to turn individual architectural features and synthesis algorithms on or off Gray or Default (default): set by higher level or global setting Check or Auto: enable feature Blank or Ignore: disable feature Copyright 169。 1997 Altera Corporation Compiler Input Files ? Design files – MAX+PLUS II ? Graphics file (.gdf), AHDL file (.tdf), VHDL file (.vhd) – 3rd Party EDA Tools ? EDIF file (.edf) – Select Vendor in EDIF Netlist Reader Settings – Library Mapping File (.lmf) required for vendors not listed ? OrCAD file (.sch), Xilinx file (.xnf) ? Assignment and Configuration File (.acf) – Controls the Compiler’s synthesis and place amp。 1997 Altera Corporation System Production Design Specification Design Entry Simulation Device Programming InSystem Verification Design Modification Compilation Timing Analysis Copyright 169。 1997 Altera Corporation ? Set up a new project – Same as Graphic Design Entry ? Enter text description – AHDL – VHDL ? Save amp。 1997 Altera Corporation Generate Symbols and Include Files ? Create symbol for higherlevel schematic capture ? Create include file for AHDL function prototype Create symbol Create include file Copyright 169。 Megafunctions ? Select ports ? Set parameters Set desired ports by clicking on Port Name and set Port Status to Used or Unused Set desired parameters by clicking on Parameter Name and set the desired value in the Parameter Value field Click on the Help button to get information about the LPM or Megafunction Copyright 169。 1997 Altera Corporation Design Entry ? Multiple design entry methods – MAX+PLUS II ? Graphic design entry ? Text design entry – AHDL, VHDL – 3rd party EDA tools ? EDIF – FPGAExpress ? OrCAD schematics, Xilinx (XNF) files ? Files can be mixed and matched in a hierachical project ? Use LPM and Megafunctions to accelerate design entry – Megawizard is an easy to use interface Copyright 169。 Programming EDIF LPM Others EDIF Verilog VHDL SDF Standard EDA Design Entry: Standard EDA Design Verification: Cadence Mentor Graphics Logic Modelling Synopsys Viewlogic Others Cadence Mentor Graphics OrCAD Synopsys Viewlogic Others MAX+PLUS II Compiler Graphic Design Entry Text Design Entry (AHDL, VHDL, Verilog HDL) Waveform Design Entry Hierachical Design Entry Floorplan Editing DesignRule Checking Logic Synthesis amp。Copyright 169。 Fitting MultiDevice Partitioning Automatic Error Location TimingDriven Compilation Timing Simulation Functional Simulation MultiDevice Simulation Timing Analysis Device Programming Copyright 169。 1997 Altera Corporation Design Entry Files MAX+PLUS II Graphic Editor MAX+PLUS II Text Editor MAX+PLUS II Symbol Editor MAX+PLUS II Floorplan Editor TopLevel File .gdf Toplevel design files can be .gdf, .tdf, .vhd, .sch, or .edf .wdf .vhd .sch .edf .xnf Graphic File Waveform File Text File Graphic File Text File Text File Imported from other EDA tools OrCAD Synopsys, ViewLogic, Mentor Graphics, etc... Xilinx Generated within MAX+PLUS II VHDL/Verilog Waveform Schematic .tdf Text File AHDL Copyright 169。 1997 Altera Corporation Add User Libraries ? Access user created libraries – Add user library directories – Set priorities Select the library directory then click on Add Library search priority can be changed. The Project directory has the highest priority, followed by the User Libraries, then by the Altera Libraries Copyright 169。 1997 Altera Corporation Symbol Editor ? Symbols can be modified with the Symbol Editor Copyright 169。 check the design – Similar to Graphic Design Entry – The file extension is .tdf or .vhd Text Design Entry Copyright 169。 1997 Altera Corporation MAX+PLUS II Compiler ? Process all design files associated with the project – Files can be created with MAX+PLUS II or 3rd party EDA Tools ? Checks for syntax errors and mon design pitfalls ? Performs logic synthesis and place amp。 route operations – Automatically generated when user enter assignments – Automatically updated when user changes assignments or backannotes project Copyright 169。 1997 Altera Corporation Synthesis Style Assignment ? Predefined frequently used groups of logic options – None (default): set by higher level or global setting – FAST: enable features – NORMAL: disable features – WYSIWYG: implement design a