【正文】 (2) graphics language. As the graphic language developed by convenience weled by the majority of engineers. There are not many trained in puter language engineers able to master the development of virtual instrument technology and applied to engineering practice in a relatively short period of time. Virtual instrument is essentially an open structure which to provide signal processing, storage and display functions by generalpurpose puter, digital signal processors, or other CPU. To achieve instrument functions from data acquisition boards, GP IB or VXI bus interface board for signal acquisition and control. According to its different ways of using the bus can be divided into the following types: (1) PC Bus plugin cardbased virtual instrument (2) parallel port virtual instruments (3) the way of GB IB bus virtual machines (4) VXI bus mode Virtual Instrument (5) PXI bus mode virtual instruments 3. Reconfigurable Data Acquisitions Systems We propose the implementation of a reconfigurable data acquisition system using FPGAs. This system operates like a reconfigurable coprocessor oriented to the capture, generation and analysis of digital signals. The bination of this hardware with a general purpose puter results in a reconfigurable virtual instrumentation system where the end user determines the software and hardware resources required for each particular application. General Description 中原工學(xué)院信息商務(wù)學(xué)院外文翻譯 12 The more essential blocks of a data acquisition system are represented in Figure 2. As an application oriented system, most of these modules must be scalable (increasing or decreasing the number of input/output pins) according to different applications. For example, the capacity of the acquisition memory varies with the requirements of the instrument. At the same time, if the device provides with enough resources, several instruments can be active simultaneously. In this case, some blocks of the structure shown in Figure 2 must be multiplied accordingly while others can be shared among instruments. For example, an unique puter interface block multiplexed in time is generally more efficient because less input/output pins are dedicated to the munication tasks. In the puter side, the software is dedicated to the storage and visualization of data, and also to the configuration and control of the hardware. The first tasks are implemented at application level and take advantage of multitask operating syste ms and their advanced graphic interfaces. The second tasks are mainly implemented as extensions of the operative systems and in this way they are closely linked to the hardware. The blocks represented in Figure 2 are briefly described in the next sections. Also, the characteristics of the configurable devices (SRAM FPGAs) required for the implementation of these blocks are indicated. Input/Output Modules The input/outputs modules conform the interface with the real world. The input/output blocks of the reconfigurable device must be bidirectional, with tristate capability and internal registers for faster capture rates. Acquisition Control Block The data capture is usually synchronized with some external or internal events and this task is developed by the acquisition control module. As a consequence, the routing of this control signals to the input/output blocks and to the internal logic bees very important. An architecture with several low skew and great fanout distribution works is mandatory for this purposes. At the same time, several inputs and outputs usually share mon control signal so a device with a peripheral bus carrying control signals is suitable for this application. Timing Blocks The timing blocks (oscilator, timers and counters) provides internal control signals to 中原工學(xué)院信息商務(wù)學(xué)院外文翻譯 13 the data acquisition system. Special attention was dedicated to the design of counters in order to reach maximum operating frequencies. Memory Blocks The memory blocks operate as a temporary storage of the acquired/generated data. This memory blocks isolate the data acquisition process from the transference through the puter interface. Therefore these storage devices are implemented as dualport FIFOs with different clocks for push/pop operations. The memory blocks can be implemented like internal or external units to the FPGA. The first case is more desirable because the design offers best performance, consumes less power and is less error prone. Therefore, the FPGAs with embedded dual port memory blocks are more suitable for these purposes. Data Processing Unit The data processing unit performs a realtime preprocessing of the acquired data. This unit implements the more critical algorithms that determine the data throughput while the others can relay over software control (in the puter side). An exhaustive analysis of which algorithms must be implemented in hardware and which must be implemented in software was made for each different instrument. For example in a logic analyzer, the detection logic of the trigger patterns must be implemented in hardware for better performance meanwhile the data conversion formats of data (assembling, disassembling) can be done in the puter. Computer Interface There are two different options for the interconnection of the reconfigurable data acquisition board with the puter, one using of a direct expansion/local bus connection and the other using of a serial/parallel munications interface. In the first case, instruments with a great data throughput can be obtained but this kind