【正文】 s, IP vendors, and system houses could exchange systemlevel IP and executable specifications, and the electronic design automation industry could develop interoperable tools. Supporters of SystemC believe that the wouldbe standard has to be based on C++ because it allows capabilities to be added to it without leaving the language standard, Kunkel told JEEE Spectrum. Most software developers use C++ and many systems developers use C++ already to describe their systems at a behavioral level. But till now it has not been possible to describe hardware using the language. The developers of SystemC have solved that problem by defining new C++ class libraries and a simulation kcrne1 that bring to C++ all of the capabilities needed to describe hardware. These new classes implement new functionality, explained Kunkel. For example, bit vectorsstrings of zeros and onesand all the operations that you would do on them. The SystemC developers also provided a class of signed and unsigned numbers, the notion of a signal, and other concepts needed to model hardware. There are still some holes, however. For example, it is still not possible to synthesize a gatelevel list from a SystcmC description. Rut synthesis tools for SysteniC would he a natural result of broad acceptance of the language within the user munity, according to Kunkel. It remains to be seen whether SystemC or Superlog wins out in the end. Least desirable would be an oute like the impasse between Virology and VHDL, in which both prevailed, forcing electronic design automation vendors to support both platforms in a wasteful duplication of effort. THE VERIFICATION NIGHTMARE If today39。t familiar with what P property ishe is used to simulation and static timing. As a remedy, InnoLogic developed a symbolic simulation tool, which blends simulation and formal verification. It is a Virology simulator except instead of sending Is and Os through the logic, the too1 propagates symbol or symbols plus binary user gains improved functional coverage dong with much faster verification. To illustrate, to pletely verify a fourbit adder would require 256 binary vectorsand take 256 simulation cycles. With symbols, it takes just one cycle. Just as with formal verification, there are limits to the plexity of the circuits that symbolic simulation can pletely verily. Both have trouble with multipliers, for example. A model checker will grind and grind and never produce a result, explained Napper. But in our tool we take some symbol inputs and switch them to binary values, that reduces the job from a 32 to a 16bit multiplier. And we report to the user that we were able to verify the upper the operands. InnoLogic has announced two Versifies of symbolic simulation. ESI39。 design automation, is the extraction of useful information about ICs, chip sets, and boards from suppliers39。s customers. The cost is on a peruse basis and is a minimal US $10. 附錄 C 翻譯中文 電子設計自動化 關鍵字 電子設計自動化 ； 集成電路； VHDL 語言 ；現(xiàn)場可編程門陣列 在這個片上系統(tǒng)開始出現(xiàn)的時候，有三個問題一直困擾著集成電路設計者。因此，為了滿足時間需要，做出一個不用反復設計的設計是遙遠的目標。這樣的系統(tǒng)一般包含一個嵌入的處理器核 運行軟件調(diào)制解調(diào)器。這種不同語言的使用給描述，仿制，調(diào)試集成電路的線路和軟件的條理清晰方面都帶來了很大的不便。選為被發(fā)展的現(xiàn)有語言有 C,C++,Java 和 Verilog。第三應該由一種現(xiàn)存的方法演變而來。從 Verilog andVHDL 方面， superlog 獲得了設計中描述硬件方面的能力，例如順序邏輯，組合邏輯和多值邏輯。 davidmann 說這門語言推廣到公共領域使用是非常重要的。協(xié)同設計公司將繼續(xù)為設計程序的前景開發(fā)新的產(chǎn)品。為了使 system C 重新運行，這個組提供了一個建模平臺在他們的網(wǎng)址里免費下載。 system c 的支持者們堅信未來的標準將建立在 C++之上因為 它允許不放棄語言標準增加新的功能。對此， KUNKEL 解釋說：“這些新的類實現(xiàn)了新的性能。例如，從一個 system C 描述上仍舊不能生成一個門級的網(wǎng)表文件。 檢驗噩夢 如果說當今復雜的集成電路設計起來很困難，那么檢驗起來就更加困難。這個仿真平臺也能使設計者們嘗試運用軟件而運行 ASIC 碼?！?John 補充說“他們必須完成大量的操作以確保功能的正確性”。通常，一百萬現(xiàn)場可編程門陣列門譯成 20xx00ASIC 門。并且仿真系統(tǒng)在內(nèi)部設計過程中對設計調(diào)試非常有效。之后將寄存器傳送級編碼合成為 ASIC 門，也就是最終合成為ASIC 門?！? 除仿真之外，兩種補充的設計檢驗方法是模擬和一種正規(guī)的檢驗類型 模型檢驗。 模型檢驗的癥結是使用上的巨大困難。這種模擬工具結合了模擬和正規(guī)的檢驗。而使用符號只運行一個周期?！?napper 解釋說“但是在我們的工具中我們采取一些符號輸入并且將它們轉(zhuǎn)變?yōu)槎M制數(shù)值。 ESPXV檢驗以 verilog寫成的設計。問題發(fā)生在這里，由于一些原因。如果最終能夠完成的話 ，一些通過合成和替代產(chǎn)生的循環(huán)重復可能對于實現(xiàn)所需時序是必要的。 Dolphin運用分析結果維持所有種類的系統(tǒng)規(guī)定參數(shù)以便同時放置和運行每一個門和復振器。它以定時標記為方法，給時序特定的限制，使其不再在合成與結構設計之間重復。synchronicity 公司是這個領域的一個開拓 者。 據(jù)公司總裁 Michael Bitzko 說，問題是基于這些部件的產(chǎn)品的設計者們需要能夠迅速獲得他們的信息并且盡快將其運行在他們的設計工程，生產(chǎn)和采購中。 ECIX 標準是由位于德州 Austin 的電子設計自動化標準組織SI2 開發(fā)的。 quickdata 服務器是為查找電子部件信息的參數(shù)查詢引擎，而 quickdata 轉(zhuǎn)換器則是將包含在 PDF 數(shù)據(jù)表中的信息轉(zhuǎn)換成可用的格式。 另外該公司贊助了一個合作網(wǎng)站 ，旨在展示這項技術的用途。 基于網(wǎng)絡的電子設計的其他方面從事起來要比設計和信息管理方面進展緩慢。 websim 允許設計者使用仿真器在網(wǎng)絡上 模擬設計。仿真器在 transim 公司的六個服務器中的大農(nóng)場中運行，其中六個服務器由 sun microsystems 公