【正文】 ite different from those discussed in this chapter. The word lengths may be short (say, four or eight bits),the number of registers small, and the instruction sets limited. Performance, relatively speaking, is poor, but adequate for the task. Most important, the cost of these microcontrollers is very low, making their use cost effective. In the following pages, we consider two puter CPUs, one for a plex instructio n set puter (CISC) and the other for a reduced instruction set puter (RISC). After a detailed examination of the designs, we pare the performance of the two CPUs and present a brief overview of some methods used to enhance that performance. Finally, we relate the design ideas discussed to general digital system design. The plex instruction set puter The first design we present is for a plex instruction set puter with a nonpipelined datapath and microprogrammed control unit. We begin by describing the instruction set architecture, including the CPU register set, instruction formats, and addressing modes. The 1 CISC nature of the instruction set architecture is demonstrated by its memorytomemory access for data manipulation instructions, eight addressing modes, two instruction format lengths, and instructions that require significant sequences of operations for their execution. We design a datapath for implementing the CISC architecture. The datapath is based on the one initially described in Section 79 and incorporated into a CPU in section 810. modifications are made to the register file, the function unit, and the buses to support the present instruction set architecture. Once the datapath has been specified, a control unit is designed to plete the implementation of the instruction set architecture. The design of the control unit must involve a coordinated definition of both the hardware anization and the microprogram anization. In particular , dividing the microprogram into microroutines, while at the same time designing the sequencer with which they interact, is a key part of the design. Even the instruction fields and opposed are tied to this coordinated effort. Following the definition of the hardware and microcode anizations, we detail essential parts of the microcode and the microroutines for representative operations. Instruction set architecture Figure 101 shows the CISC register set accessible to the programmer. All registers have 16 bits. The register file has eight registers, R0 though is a special register that always supplies the value zero when it is used as a source and discards the result when it is used as a destination. In additional to the register file, there is a program counter PC and stack pointer SP. The presence of a stack pointer indicates that a memory stack is a part of the architecture . the final register is the processor status register PSR, which contains information only in its rightmost the five bits。在通用計算機開始的第一章， CPU 作為處理器的一部分被屏蔽了。字長也許更短，（或者說 4或 8個字節(jié)），編制數(shù)量少，指令集有限。在詳細的設(shè)計檢查之后，我們比較了兩個 CPU 的性能，并提交了用來提高性能的一些 方法的簡要概述。復雜指令集計算機（ CISC）的指令集構(gòu)架的性質(zhì)是通過它的內(nèi)存到內(nèi)存進行數(shù)據(jù)存取操作指示 8 個處理模式，兩長指令格式和指令集，來為它們的執(zhí)行獲得重要的運行序列。 一旦數(shù)據(jù)路徑被明確，被設(shè)計的一個控制單元就去完成指令集構(gòu)架的執(zhí)行。以下是硬件和微代碼組織的定義，我們詳細描述的是為運行代表的微型代碼個微型線路的基本部分。 R0 是一個寄存器，當它被作為目的來使用，作為來源和拋棄的結(jié)果來使用時她總是提供零價值。另外，一個存儲中斷使得 EI處在 4 的位置上。另外，這些狀態(tài)位受到被列開的操作的影響。接下去的兩個是 MODE 和 S，是被用來確定運算的地址。當這些位是 00 時 ，要么是沒有被要求的操作要么是被 OPCODE 隱含的操作的位置。因為有了一個操作， MODE 領(lǐng)域就會為獲得它而指定處理方式。為獲得最大的靈活性，這個切換數(shù)額是只針對像來源運算一樣的的運算。 MODE 的前兩位指定了 4 中不同的處理類型：注冊、立即、索引以及相關(guān)的程序計數(shù)器 PC。對指令的注冊類型來說， MONE(2:1)=00 和這個 W字母是不需要 的。通用指令的所有領(lǐng)域，其中包括 S和 SRC，被用于為所有指令的案件。注冊轉(zhuǎn)換為處理結(jié)果的描述在在表 2 第四次和第五次欄已給出了。對于這個類型的所有指令，目的地的地址（而不是操作）成為新的地址放置程序計數(shù)器 PC 里。一些不會顯示的 操作是多余的。有 8 個處理模式和兩種不同長度的指令格式。該數(shù)據(jù)路徑顯示在第 810節(jié)，和新的數(shù)據(jù)路徑，是給出的圖 106的基礎(chǔ)上進行修改的。因此，更多的臨時存儲需要通過微程序來使用。如前所述，編程 R0 提供的是一個常數(shù) R1 到 R7可提供給程序員使用，編程 R8到 R15 提供通用的臨時存儲被微程序使用，最后 4個編程， R12 到 R15 具有特殊的用途：保持簡單的微型代碼，標準的位置對存儲的操作和被為大多數(shù)指令而執(zhí)行的微代碼所使用的地址來說是必不可少的。此外，允許注冊地址的靈活性通過 DST 成為來源和通過 SRC成為目的地，他們是需要操作結(jié)果的允可來直接存放在內(nèi)存中。雖然在微指令水平上的地址從 3個減少到 2 個是沒必要的，但對在微指令中的注 冊地址和指令格式中的匹配使用的登記領(lǐng)域的位的數(shù)量的減少還是必要的。如果一個指令地址被選定了，不管它是被增加的 4 倍 2 比 1 多功能器確定的 DST 還是 SRC。登記檔案結(jié)果的一個特征顯示在圖 104( b)中。 控制單元還具有廣泛的跳躍和有條件的分支能力，包括微型子路線的一個層次。我們研究任何形式的風險，像軟件和硬件一頁提出每個解