【正文】 n frequency between the reference input and the feedback input. Frequency correctint is akin to “rough” tunint and occurs when Fvco is less than or greater than 2 Fref. Phase correction is the “fine” tuning and occurs when Fvco Fref2 Fvco. The Phase/Frequency Detector detects differences in phase and frequency beween the reference and feedback inputs and generates pensating “Up” and “Down” signals depending on whether the feedback frequency is lagging or leading the reference frequency respectively. These control signals are then passed through a charge pump and a loop filter to generate a conrrol voltage, which controls a VCO. The frequency of this oscillator is dependent on the Vctrl input. At steady state, the VCO frequency is: Fvco= Frefns. Jitter can be classified into three categories: cyclecycle jitter, period jetter, and longterm jitter. Cyclecycle jitter is the difference in a clocl’s period from one cycle to the next. This kind of jitter is the most difficult to measure and usually requires a Tining Interval Analyzer. Period jitter, also called shortterm jitter, is a change in a clock’s output transition from its ideal position over consecutive clock edges. Note that in the case of shortterm jitter, the variation of the rising edge of clock from the ideal positon is measured and expressed in units of time or frequrncy. Longterm jitter is a change in a clock’s output transition from its ideal position over “many” cycles. The term ”many” depends on the application and the frequency. For PC motherboard and graphics applications, this term “many” usually refers to 1020 microseconds. For other applications, it may be different. Causes of Jitter There are four primary causes of jitter as indicated below: Random mechanical noise from vibrations of the crystal Clock jitter affects almost all highspeed synchronous systems. Common applications affected by jitter are PC motherboards, graphics cards, and munications equipment. Skew Skew is the variation in arrival time of two signals specified to arrive at the same time. Skew is posed of two parts, the output skew of the driving device, and board design skew, caused by layout variation of board traces. Clock Driver Skew (Intrinsic Skew) is the amount of skew caused by the clock drivices. Skew occurs on the output of the buffer devices because of the difference is attributed to differences in output loading. Skew in PLLbased devices can be very small, since a PLLbased device can be adjusted to pensate for differences in output loading. Board Design Skew (Extrinsic skew) is the amount of skew caused by board layout issues such as:Transmission Line Termination: With the extremely fast edge rates in today’s clock drivers, traces longer than 4 inches are considered transmission lines. Without proper termination, these lines will exhibit transmission line effects like voltage reflections, which will cause skew.Why is skew important? In highspeed systems, clock skew forms an important ponent of timing margin. A skew of 1 ns is a significant portion of a 15ns cycle time. If the timing budget does not allow for skew, it is highly likely that the system will perform unreliably.The simplest method of measuring skew between two outputs of a device is to display both waveforms in a dualchannel oscilloscope and measure the difference between the rising edges. This is the skew.Tolerance/AccuracyTolerance/Accuracy is a measure of how close the part operates to the specified (nominal) freqency,typically referenced at ambient temperature (25oC+/5oC). For example, if a part is specified with a output, and the longterm (userdefined) average of its output frequency is at ambient temperature, the part has +40 ppm (parts per million) accuracy. Frequency tolerance is affected or controlled by controlling the accuracy of the manufacturing and calibrating process for the crystal.Stability Stability is a parameter usually associated with crystals and oscillators. Stability is defined as the variation in operating frequency from the ambient temperature frequency (frequency tolerance value) over the operating temperature range and is expressed in ppm. This parameter is specified with a maximum and minimum frequency deviation, expressed in percent or parts per millon. Why is stability important? Stability may cause marginal operation of a design over plete temperature range, if it is not accounted for in the design.AgingAging is defined as the systematic change in frequency over time due to internal changes in crystal/oscillator. It is usually expressed in ppm/year, and may be incorporated in the Stability spec, if it is not drawn out separately. It is a paramter usually associated with crystal oscillators. New crystals age faster than old crystals.SlewThe rate of change of voltage or frequency is called Slew. Slewis usually measured on the rising and falling edges of digital signals. However, rise times and fall times are more monly specified, instead of slew, in vendor’s catalogs. Recently, with the advent of lowpower devices, slew is being used to define a rate of change of frequency.Duty CycleDuty Cycle is the ratio of the output high time to the total cycle time. It is expressed as a percentage. 50% is the ideal duty cycle, though most clock manufacturers specify duty cycles from 40%~60%. Duty cycle is important in systems that use both the rising and falling clock edges.Duty cycles can be expressed for both TTL and CMOS devices. For TTL devices, since the voltage swing is from 0V~3V,the high time is measured at the level. For CMOS devices, since the voltage swing is from 0Vdd Volts, the high time is measured at Vdd/