【正文】 exception to this occurs during the execution of a readmodifywrite instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SET, and the bitwise MOV operation). During the read cycle of the readmodifywrite instruction, it is the contents of the Port Data register, not the state of the Port pins themselves, which is read. Because the Crossbar registers affect the pinout of the peripherals of the device, they are typically configured in the initialization code of the system before the peripherals themselves are configured. Once configured, the Crossbar registers are typically left alone. Once the Crossbar registers have been properly configured, the Crossbar is enabled by setting XBARE () to a logic 1. Until XBARE is set to a logic 1, the output drivers on Ports 0 through 3 are explicitly disabled in order to prevent possible contention on the Port pins while the Crossbar registers and other registers which can affect the device pinout are being written. The output drivers on Crossbarassigned input signals (like RX0, for example) are explicitly disabled。 a logic 0 in will configure the output mode of to OpenDrain. All Port pins default to OpenDrain output. The PnMDOUT registers control the output modes of the port pins regardless of whether the Crossbar has allocated the Port pin for a digital peripheral or not. The exceptions to this rule are: the Port pins connected to SDA, SCL, RX0 (if UART0 is in Mode 0), and RX1 (if UART1 is in Mode 0) are always configured as OpenDrain outputs, regardless of the settings of the associated bits in the PnMDOUT registers. A Port pin is configured as a digital input by setting its output mode to “OpenDrain” and writing a logic 1 to the associated bit in the Port Data register. For example, is configured as a digital input by setting to a logic 0 and to a logic 1. If the Port pin has been assigned to a digital peripheral by the Crossbar and that pin functions as an input (for example RX0, the UART0 receive pin), then the output drivers on that pin are automatically disabled. In addition to the external interrupts /INT0 and /INT1, whose Port pins are allocated and assigned by the Crossbar, and can be configured to generate edge sensitive interrupts。高端口（ PP P6 和 P7）只能按字節(jié)尋址。系統(tǒng)設(shè)計者控制數(shù)字功能的引腳分配，只受可用引腳數(shù)的限制。 優(yōu)先權(quán)交叉開關(guān)譯碼器，或稱為“交叉開關(guān)”，按優(yōu)先權(quán)順序?qū)⒍丝?0 – 3 的引腳分配給器件上的數(shù)字外設(shè)（ UART、 SMBus、 PCA、定時器等）。例如，如果 UART0EN位（ ）被設(shè)置為邏輯‘ 1’，則 TX0 和 RX0 引腳將分別被分配到 和 。例如，不能為 UART0 功能只分配 TX0 引腳而不分配 RX0 引腳。向端口數(shù)據(jù)寄存器（ 或相應(yīng)的端口位）寫入時對這些引腳的狀態(tài)沒有影響。 因為交叉開關(guān)寄存器影響器件外設(shè)的引腳分配，所以它們通常在外設(shè)被配置前由系統(tǒng)的初試化代碼配置。 被交叉開關(guān)分配給輸入信號（例如 RX0）的引腳所對應(yīng)的輸出驅(qū)動器應(yīng)被明確禁止；以保證端口數(shù)據(jù)寄存器和 PnMDOUT 寄存器的值不影響這些引腳的狀態(tài)。在漏極開路方式，向端口數(shù)據(jù)寄存器中的相應(yīng)位寫邏輯‘ 0’將使端口引腳被驅(qū)動到 GND，寫邏輯‘ 1’將使端口引腳處于高阻狀態(tài)。所有端口引腳的缺省方式均為漏極開路。例如，設(shè)置 為邏輯‘ 0’并設(shè)置 為邏輯‘ 1’即可將 配置為數(shù)字輸入。如果對應(yīng)的中斷被允許，將會產(chǎn)生一個中斷， CPU將轉(zhuǎn)向?qū)?yīng)的中斷向量地址。對于端口 1 的引腳，將引腳配置為模擬輸入時上拉部件也被禁止，見下面的說明。將一個端口引腳配置為模擬輸入的過程如下： 1． 禁止引腳的數(shù)字輸入路徑。 3． 使交叉開關(guān)在為數(shù)字外設(shè)分配引腳時跳過該引腳。 在 本例中，我們將配置交叉開關(guān)，為 UART0、 SMBus、 UART /INT0 和 /INT1分配端口引腳（共 8 個引腳）。 2． 將外部存儲器接口配置為復(fù)用方式并使用低端口，有： PRTSEL = 0， EMD2 = 0。 SMBus 的優(yōu)先權(quán)次之，所以 被分配 給 SDA， 被分配給 SCL。下一個未被跳過的引腳 被分配給 RX1。 5． 我們將 UART0 的 TX 引腳、 UART1 的 TX 引腳（ TX1， ）、 ALE、 /RD、/WR（ P0.[7:3]）的輸出設(shè)置為推挽方式，通過設(shè)置 P0MDOUT = 0xF1