【正文】 y problems in CPU design and the solve in the clue of minimumsystem dilatation, and then it shows the toplevel framework and module interfaces. The final simulation and verification shows that the design works correctly and stably on Altera FPGA series. Keywords: RISC MIPS 32bit CPU Pipeline 北京理工大學(xué)本科生畢業(yè)設(shè)計（論文） III 目 錄 摘 要 ............................................................................................................................. I 第 1 章 CPU 體系結(jié)構(gòu)概述 ......................................................................................... 1 前言 ..................................................................................................................... 1 CISC 處理器與傳統(tǒng)處理器設(shè)計思想 ............................................................... 1 CISC 處理器的瓶頸 ........................................................................................... 2 RISC 微處理器 .................................................................................................. 3 MIPS 處理器 ..................................................................................................... 4 本設(shè)計的處理器 ................................................................................................. 5 小結(jié) ..................................................................................................................... 5 第 2 章 MIPS 處理器結(jié)構(gòu)與技術(shù) ............................................................................... 6 MIPS 指令集簡介 ............................................................................................ 6 CPU的幾種典型結(jié)構(gòu) .................................................................................... 14 單周期 CPU .......................................................................................... 14 多周期 CPU .......................................................................................... 16 流水線 CPU .......................................................................................... 18 更高性能 CPU 的結(jié)構(gòu) ....................................................................... 22 小結(jié) .......................................................................................................... 24 第 3 章 MIPS 處理器的實現(xiàn) ...................................................................................... 25 本設(shè)計的基本原則與方法 ............................................................................... 25 自頂而下設(shè)計法與最小系統(tǒng)擴展法 ............................................... 25 本設(shè)計的實現(xiàn)方法 .............................................................................. 26 實現(xiàn)平臺 ........................................................................................................... 27 可編程邏輯器件與 FPGA 簡介 ........................................................ 27 FPGA 的特點 ....................................................................................... 27 本設(shè)計的實現(xiàn)平臺 .............................................................................. 28 ALU組件設(shè)計 ................................................................................................. 28 超前進(jìn)位加法器設(shè)計 ......................................................................... 28 并行乘法器樹設(shè)計 .............................................................................. 30 北京理工大學(xué)本科生畢業(yè)設(shè)計（論文） IV 單周期最小 CPU系統(tǒng)設(shè)計 ............................................................................. 32 CPU結(jié)構(gòu)的流水化 .......................................................................................... 45 數(shù)據(jù)相關(guān)與數(shù)據(jù)前推網(wǎng)絡(luò) ............................................................................... 49 控制相關(guān)與跳轉(zhuǎn)網(wǎng)絡(luò) ....................................................................................... 56 完整指令集的實現(xiàn) .......................................................................................... 60 控制單元的擴展 .................................................................................. 60 ALU 的擴展 .......................................................................................... 62 Register 的擴展 ................................................................................... 65 DataMemory 的擴展 ........................................................................... 65 乘除法的超流水處理 .......................................................................................... 68 流水線中斷處理的實現(xiàn) ............................................................................... 70 中斷網(wǎng)絡(luò)接管 PC 的兩入兩出法 ..................................................... 70 中斷網(wǎng)絡(luò)的具體實現(xiàn) ......................................................................... 72 小結(jié) .................................................................................................................... 79 第 4 章 CPU 頂層結(jié)構(gòu)與模塊級功能簡介 ................................................................ 80 第 5 章 流水線 CPU 的仿真 ........................................................................................ 91 流水線 CPU的指令仿真 .................................................................................... 91 算術(shù)運算指令 ...................................................................................... 91 移位指令 ............................................................................................... 92 乘法與除法指令 .................................................................................. 94 立即數(shù)運算指令 .................................................................................. 96 Load/Store 指令 ................................................................................... 97 跳轉(zhuǎn)指令 ............................................................................................... 98 應(yīng)用綜合示例 —— 中斷處理程序 ................................................................. 98 小結(jié) ............................................................................................................... 101 第 6 章 匯編語言開發(fā)環(huán)境簡述 ......................................................