英語(yǔ),i2c總線規(guī)范21部分-全文預(yù)覽
【正文】 links a number of Hsmode transfers, separated by repeated START conditions (Sr). Data transfer format in Hsmode. A plete Hsmode transfer. Switching from F/S to Hsmode and backAfter reset and initialization, Hsmode devices must be in Fastmode (which is in effect F/Smode as Fastmode is downward patible with Standardmode). Each Hsmode device can switch from Fast to Hsmode and back and is controlled by the serial transfer on the I2Cbus.Before time t1 in , each connected device operates in Fastmode. Between times t1 and tH (this time interval can be stretched by any device) each connected device must recognize the “S 00001XXX A” sequence and has to switch its internal circuit from the Fastmode setting to the Hsmode setting. Between times t1 and tH the connected master and slave devices perform this switching by the following actions.The active (winning) master:1. Adapts its SDAH and SCLH input filters according to the spike suppression requirement in Hsmode.2. Adapts the setup and hold times according to the Hsmode requirements.3. Adapts the slope control of its SDAH and SCLH output stages according to the Hsmode requirement.4. Switches to the Hsmode bitrate, which is required after time tH.5. Enables the current source pullup circuit of its SCLH output stage at time tH. The nonactive, or losing masters:1. Adapt their SDAH and SCLH input filters according to the spike suppression requirement in Hsmode.2. Wait for a STOP condition to detect when the bus is free again. All slaves:1. Adapt their SDAH and SCLH input filters according to the spike suppression requirement in Hsmode.2. Adapt the setup and hold times according to the Hsmode requirements. This requirement may already be fulfilled by the adaptation of the input filters.3. Adapt the slope control of their SDAH output stages, if necessary. For slave devices, slope control is applicable for the SDAH output stage only and, depending on circuit tolerances, both the Fast and Hsmode requirements may be fulfilled without switching its internal circuit.At time tFS in , each connected device must recognize the STOP condition (P) and switch its internal circuit from the Hsmode setting back to the Fastmode setting as present before time t1. This must be pleted within the minimum bus free time as specified in Table 5 according to the Fastmode specification. Hsmode devices at lower speed modesHsmode devices are fully downwards patible, and can be connected to an F/Smode I2Cbus system (see ). As no master code will be transmitted in such a configuration, all Hsmode master devices stay in F/Smode and municate at F/Smode speeds with their currentsource disabled. The SDAH and SCLH pins are used to connect to the F/Smode bus system, allowing the SDA and SCL pins (if present) on the Hsmode master device to be used for other functions. Hsmode devices at F/Smode speed(1) Bridge not used. SDA and SCL may have an alternative function.(2) To input filter.(3) The currentsource pullup circuit stays disabled.(4) Dotted transistors are optional opendrain outputs which can stretch the serial clock signal SCL. Mixed speed modes on one serial bus systemIf a system has a bination of Hs, Fast and/or Standardmode devices, it’s possible, by using an interconnection bridge, to have different bit rates between different devices (see Figs 24 and 25).One bridge is required to connect/disconnect an Hsmode section to/from an F/Smode section at the appropriate time. This bridge includes a level shift function that allows devices with different supply voltages to be connected. For example F/Smode devices with a VDD2 of 5 V can be connected to Hsmode devices with a VDD1 of 3 V or less (. where VDD2 179。 The only difference between Hsmode slave devices and F/Smode slave devices is the speed at which they operate. Hsmode slaves have opendrain output buffers on the SCLH and SDAH outputs. Optional pulldown transistors on the SCLH pin can be used to stretch
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