【正文】 ta2 = 3239。h0004。 539。b10001: data2 = 3239。end endmodule符號擴展器：將指令中16位有符號數(shù)擴展成32位有符號數(shù)符號代碼：module signal_extend( input [15:0] in, output [31:0] out )。為準(zhǔn)備執(zhí)行。 end根據(jù)分治設(shè)計策略，確定模塊間的連接關(guān)系，端口方向及寬度，將每一模塊通過控制信號聯(lián)系起來，最終形成完整的數(shù)據(jù)通路。wire RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite,ALUSrc, RegWrite,zero。wire [2:0] ALUctrl。 mux (5) mux1_datareg(.in0(instruction[20:16]), .in1(instruction[15:11]), .out(addr_regwrite), .ctrl(RegDst))。ALU ALU(.in1(data1),.in2(ALU2),.ALU_out(ALUout),.ctrl(ALUctrl),.zero(zero))。left_shift lshift2(.in(instruction),.out(jumpaddr_l))。mux (32) mux4_PCnew(.in0(PCnew),.in1(add2out),.out(mux4out),.ctrl(zero amp。PC PC0(.clk(clk),.reset(reset),.PCnext(PCnext),.PC(PC))。b100011, 539。其中immt($t7)指向的內(nèi)存地址中存的數(shù)為32’b0101 // sw $s0,immt($t7) 3239。b00101, 1639。b000000, 539。b00000, 639。b000000, 539。b00000, 639。b000000, 539。b00000, 639。b000000, 539。b00000, 639。b000000, 539。b00000, 639。b000100, 539。其中$s0=$s2=32’h000c跳轉(zhuǎn)：J 10003239。第五部分 性能評估：綜合結(jié)果：面積報告：****************************************Report : areaDesign : topVersion: Date : Tue Sep 4 15:27:35 2012****************************************Library(s) Used: typical (File: /export/homeO1/smic018/)Number of ports: 103Number of nets: 634Number of cells: 156Number of references: 30Combinational area: Nonbinational area: Net Interconnect area: Total cell area: Total area: 時序報告：****************************************Report : timing path full delay max max_paths 1Design : topVersion: Date : Tue Sep 4 15:27:46 2012****************************************Operating Conditions: typical Library: typicalWire Load Model Mode: top Startpoint: PC0/PC_reg[21] (rising edgetriggered flipflop clocked by clk) Endpoint: data_regwrite[25] (output port clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library top smic18_wl10 typical Point Incr Path clock clk (rise edge) clock network delay (ideal) PC0/PC_reg[21]/CK (DFFRHQX4) r PC0/PC_reg[21]/Q (DFFRHQX4) r PC0/PC[21] (PC) r ins_reg/pc[21] (instruction_reg) r ins_reg/U53/Y (NOR2X4) f ins_reg/U37/Y (NAND4X4) r ins_reg/U55/Y (NOR2X4) f ins_reg/U56/Y (NAND2X4) r ins_reg/U38/Y (BUFX20) r ins_reg/U31/Y (NOR2X4) f ins_reg/ins[28] (instruction_reg) f con/in[2] (control) f con/U29/Y (NOR2X4) r con/U33/Y (NAND3X4) f con/U34/Y (NOR2X4) r con/RegDst (control) r mux1_datareg/ctrl (mux_N5) r mux1_datareg/U1/Y (BUFX20) r mux1_datareg/U10/Y (OAI2BB2X4) r mux1_datareg/out[1] (mux_N5) r U25/Y (BUFX16) r data_reg/writeaddr[1] (data_reg) r data_reg/U368/Y (NAND2BX4) r data_reg/U365/Y (INVX8) f data_reg/U362/Y (INVX8) r data_reg/U265/Y (OR2X4) r data_reg/U101/Y (AND2X4) r data_reg/U3