【正文】 irst bit, which selects the address source, the addresses from the microinstruction contain four bits so that all 16 registers can be reached. The final change to the register file is to replace the storage elements for R0 in the file with open circuits on the lines that were their inputs and with constant zero valves on the lines that were their outputs. A symbol for the resulting register file is show in Figure 104(b). We find that, based on the eight shift instructions provided, the shifter from section 810, needs to be modified. The modifications involve the end bits of the shift logic. For logical shifts, a 0 is inserted, as before. For the right arithmetic shift, she sign bit is the ining bit, and for the left arithmetic shift, 0 is the ining bit. Rotates require that the bit from the opposite end of the shifter be fed around. Finally, rotates with carry require that the carry flipflop output be provide as an input on both ends of the shifter. The inputs are furnished by two 4t01 multiplexers, MUX R and MUX L, added to a basic 16bit shifter, all shown in Figure 105(a). also, the appropriate end bits from the input operand must be sent to the carry flipflop. A 2to1 multiplexer MUX SO selects the end bit to pass to the carry flipflop C. the symbol for the new shifter, which replaces the basic shifter from section 810, appears in Figure 105(b), FS3, FS2, FS1, and FS0 from the FS field drive the control inputs S3, S2, S1 and S0, respectively. All modifications to the original datapath are represented in Figure 106. As a part of the design process, the new datapath needs to be checked to make sure that it has all of the capabilities necessary for implementing the instruction set and addressing modes .Certainly ,some decisions have been made that have not been discussed. For example, there is no dedicated multiplication or division hardware, so these operations must be implemented by microprograms controlling the datapath. 16 Microprogrammed Control Organization The microgrammed control unit acpanies the datapath of Figure 106 in Figure 107. The control consists of four principal parts. One is the control unit registers : the instruction register IR, the program counter PC, and the stack pointer SP. In some designs the PC and SP are logically included in the register file and thus are a part of the datapath .Here, since they are separate from the register file and are used primarily for program control ,we haveincluded them with the control . Sequencing within the control unit is provides by the microsequencer , which contains two registers: the control address register CAR and the subroutine branch register SBR. The program counter for the microprogram , the CAR simply counts up to the next address in sequence or loads in parallel . With a parallel load , the address can be set to any value and the nextaddress es from three source including the nextaddress field in the current microinstruction. Microroutines have subroutines, just as programs do. To distinguish them, we call subroutines for microprograms microsubroutines. The SBR is used to store the next address for the CAR at the time a microsubroutine in order to return microprogram execution to the 17 next microinstruction in the calling microroutine. The final part of the control unit is the instruction decode, which consists of binational logic and is also a next address source for the CAR. Microprogram structure We approach the microprogram design top down. The top level consists of an ASMlike chart giving a flow of microroutines. These routines have labels similar to the stages in the pipelined CPU in section 811. in this case, however, rather than being performed in a single clock with binational logic, the routines require the use of the same hardware over multiple cycles. The flow between and, to same extent, within the routines is intimately tied to the instructions and their decoding. Since the mapping ROM can be used for branching simultaneously with a format A data transfer or manipulation operation, it is convenient to control the flow between microroutines entirely by using the mapping ROM. This flow is shown in Figure 108。 8 圖 5 參考文獻(xiàn) [1]． DIETMEYER， D． L．， Logic Design ofDigital Systems,3rd ed． Boston， MA： Allvn． Bacon， 1988． [2]． MANO， M． M． Computer Engineering： Hardware Design． Englewood Cliffs,NJ： Prentice Hall， 1988． [3]． HAMACHER， V C．， VRANESIC， Z． G， AND ZAKY’ S． G． Computer Organization, 3rd ed． New York， Ny． McGraw— Hill， 1990． 9 [4]． HENNESSY工 L．， AND PATTERSON， D． A． Computer Architecture： A Quantitative Approach,2nd ed． San Francisco， CA： Man Kaufmann， 1996． [5]． KANE． G．． AND HEINRICH， 1． MIPS RISc Architecture． Englewood Cliffs,NJ： Prentice Hall， 1992． [6]． SPARC INTERNATIONAL． INC． The SP4尺 C Architecture Manual： Version＆ Englewood Clifts,NJ： Prentice Hall． 1992． [7]． MANO． M． M． Computer System Architecture,3rd ed． Englewood Cliffs,NJ： Prentice Hall． 1993． CENTROL PROCESSING UNIT DESIGNS ABSTRACT The CPU is the key ponent of a digital puter. Its purpose is to decode instruction receied from memory and perform transfers, arithmetic, logic, and control operations with data stored in internal registers, memory, or I/O interface units. Externally, the CPU provides one or more buses for transferring instructions, data, and control information to and from ponents connected to it. In the generic puter at the beginning of chapter 1, the CPU is a part of the processor and is heavily shaded. CPUs, however, may also appear in puters. Small, relatively simple puters called microcontrollers are used in puters and in other digital systems to perform limited or specialized tasks. For example, a microcontroller is present in the keyboard and in the monitor in the generic