【正文】 d above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly. Program Memory Lock Bits 5 On the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection Modes(1) Program Lock Bits LB1 LB2 Protection Type 1 U U No program lock features. 2 P U Further programming of the Flash is disabled. 3 P P Same as mode 2, also verify is disabled. Note: 1. The Lock Bits can only be erased with the Chip Erase operation Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the onchip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. and should be set to ’0’ if no external pullups are used, or set to ’1’ if external pullups are used. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a 6 hardware reset. Reset redefines the SFRs but does not change the onchip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. and should be set to ’0’ if no external pullups are used, or set to ’1’ if external pullups are used. Programming The Flash The AT89C2051 is shipped with the 2 Kbytes of onchip PEROM code memory array in the erased state (., contents = FFH) and ready to be programmed. The code memory array is programmed one byte at a time. Once the array is programmed, to reprogram any nonblank byte, the entire memory array needs to be erased electrically. Internal Address Counter: The AT89C2051 contains an internal PEROM address counter which is always reset to 000H on the rising edge of RST and is advanced by applying a positive going pulse to pin XTAL1. Programming Algorithm: To program the AT89C2051, the following sequence is remended. 1. Powerup sequence: Apply power between VCC and GND pins Set RST and XTAL1 to GND With all other pins floating, wait for greater than 10 milliseconds 2. Set pin RST to ’H’ Set pin to ’H’ 3. Apply the appropriate bination of ’H’ or ’L’ logic levels to pins , , , to select one of the programming operations shown in the PEROM Programming Modes table. To Program and Verify the Array: 4. Apply data for Code byte at location 000H to to . 5. Raise RST to 12V to enable programming. 6. Pulse once to program a byte in the PEROM array or the lock bits. The bytewrite cycle is selftimed and typically takes ms. 7. To verify the programmed data, lower RST from 12V to logic ’H’ level and set pins to to the appropiate levels. Output data can be read at the port P1 pins. 8. To program a byte at the next address location, pulse XTAL1 pin once to advance the 7 internal address counter. Apply new data to the port P1 pins. 9. Repeat steps 5 through 8, changing data and advancing the address counter for the entire 2 Kbytes array or until the end of the object file is reached. 10. Poweroff sequence: set XTAL1 to ’L’ set RST to ’L’ Float all other I/O pins Turn Vcc power off Data Polling: The AT89C2051 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the plement of the written data on . Once the write cycle has been pleted, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The Progress of byte programming can also be monitored by the RDY/BSY output signal. Pin is pulled low after goes High during programming to indicate BUSY. is pulled High again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed code data can be read back via the data lines for verification: 1. Reset the internal address counter to 000H by bringing RST from ’L’ to ’H’. 2. Apply the appropriate control signals for Read Code data and read the output data at the port P1 pins. 3. Pulse pin XTAL1 once to advance the internal address counter. 4. Read the next code data byte at the port P1 pins. 5. Repeat steps 3 and 4 until the entire array is read. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire PEROM array (2 Kbytes) and the two Lock Bits are erased electrically by using the proper bination of control signals and by holding low for 10 ms. The code array is written with all 1s in the Chip Erase operation and must be executed before any nonblank memory byte can be reprogrammed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 001H, and 002H, except that and must be pulled to a