【正文】 ） /INT0（外部中斷 0） /INT1（外部中斷 1） T0（記時(shí)器 0外部輸入） T1（記時(shí)器 1外部輸入） /WR（外部數(shù)據(jù)存儲(chǔ)器寫(xiě)選通） /RD（外部數(shù)據(jù)存儲(chǔ)器讀選通） RST：復(fù)位輸入。在平時(shí)， ALE端以不變的頻率周期輸出正脈沖信號(hào)，此頻率為振蕩器頻率的1/6。此時(shí)， ALE只有在執(zhí)行 MOVX， MOVC指令是 ALE才起作用。在由外部程序存儲(chǔ)器取指期間，每個(gè)機(jī)器周期兩次 /PSEN有效。在FLASH編程期間，此引腳也用于施加 12V編程電源（ VPP）。 用戶(hù)還可以采用外部時(shí)鐘，在這種情況下，外部時(shí)鐘脈沖接到 XTAL1部 時(shí)鐘發(fā)生器的輸入端， XTAL2則懸空。 (3)要給“三態(tài)輸出鎖存器”分配一個(gè)端口地址，也就是給 OE線(xiàn)上送一個(gè)地址譯碼器輸出信號(hào)。 CPU 響應(yīng)中斷后，應(yīng)在中斷服務(wù)程序中使 OE 線(xiàn)變?yōu)楦唠娖?，以提?A/D 轉(zhuǎn)換后的數(shù)字量。 25 圖 310 ADC0809與 AT89C51接口電路 聲光報(bào)警與 LED 顯示 聲光報(bào)警單元 作為煤氣泄露測(cè)試裝置，聲光報(bào)警部分不可缺少，當(dāng)檢測(cè)到瓦斯氣體在空氣中的所占的比例超標(biāo)時(shí)，就應(yīng)該通過(guò)聲光方式發(fā)出警報(bào)，防止由于瓦斯氣體含量過(guò)高而發(fā)生的意外事故。 聲光報(bào)警單元與單片機(jī)的連接圖如下： P P P P P P P P P P P P P P P X T A L 2X T A L 1R X DT X DR S TV S SIN T 0WRP RDP P P ALEA T 8 9C 51紅黃綠R3R4R5Q58 55 0R21KR31 0KV C CU 13B U Z Z E R 圖 311 聲光報(bào)警電路 LED 顯示 LED數(shù)碼顯示器是一種由 LED發(fā)光二極管組合顯示字符的顯示器件。 P口為高電位或高阻狀態(tài)發(fā)光管暗的時(shí)候電流是從電源正 —— 上拉電阻 —— P口，這時(shí) LED無(wú)電流流過(guò)， P口為低電位，限流電阻上流過(guò)電流全部從 P口流入。 本設(shè)計(jì)通過(guò)觀察 LED數(shù)碼顯示器顯示瓦斯?jié)舛戎?，判斷瓦斯?jié)舛戎凳欠癯^(guò)上限值，如果超過(guò)，自動(dòng)報(bào)警。 //AD采集控制引腳 sbit ADC_STR = P3^4。 //數(shù)碼管控制引腳 31 sbit LED2 = P2^6。 //指示燈引腳 sbit LED_G = P2^0。 i++)。 //啟動(dòng)轉(zhuǎn)換 ADC_ALE=0。 //等待轉(zhuǎn)換結(jié)束 ADC_OE=1。 //返回結(jié)果 } void display(unsigned char ptr[]) { static unsigned char data i。 //關(guān)顯示 P2=P2 amp。 P2=P2 | hang[i]。 unsigned char data baifenshu[4]。 //關(guān)閉顯示 //端口初始化 P2=0xff。 // ADC_OE=0。baifenshu)。//計(jì)算 放大到 0－1000，注 意化簡(jiǎn)，不然會(huì)計(jì)算溢出得不到正確結(jié)果 //ad_shuju*1000/255。 //取百分比個(gè)位（帶小數(shù)點(diǎn)） baifenshu[3]=tmp%10。 for(t=0。 } } LED_G=1。 } } } 35 致 謝 首先，我要感謝 *************大學(xué)，感謝電氣系對(duì)我四年的培養(yǎng)，讓我學(xué)到了許許多多的知識(shí)，感謝各位老師在這四年里對(duì)我的關(guān)懷與照顧，在此致以我深深的謝意。你 們的鼓勵(lì)和幫助永遠(yuǎn)是我前進(jìn)的動(dòng)力。s accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, e from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is deposited, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The 40 content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 onechip puters, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of . This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other puters, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is manded. There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of puter. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS51 series onechip puter and general puter disposes the way in addition. General puter for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of 41 Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three abovementioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. 8051 onechip puter have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate twoway mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction