【正文】 進行數(shù)據(jù)處理就可求得過程的數(shù)學(xué)模型。
產(chǎn)生專門信號的發(fā)生器多種多樣，下面介紹常用的階越響應(yīng)曲線法來辨識過程的數(shù)學(xué)模型。當(dāng)下水箱的液位等于給定值，且上、中水箱的液位基本不變時，把調(diào)節(jié)器由手動切換為自動，使系統(tǒng)進入自動運行狀態(tài)。經(jīng)過一定調(diào)節(jié)時間后,水箱液位重新進入平衡狀態(tài)。 記錄階躍響應(yīng)參數(shù)(間隔30s采集數(shù)據(jù)):171319281420391521410162251117236121824 中水箱階躍響應(yīng)數(shù)據(jù) ：控制調(diào)節(jié)閥開度,使初始開度OP1=40,等到水箱的液位處于平衡位置時。所以使用MATLAB軟件對實驗數(shù)據(jù)進行處理，根據(jù)最小二乘法原理和實驗數(shù)據(jù)對響應(yīng)曲線進行最佳擬合后，再計算水箱模型。p=polyfit(x, y,5)。39。在MATLAB的命令窗口輸入曲線擬合指令：x=0:30:420。yi=polyval(p, xi)。階躍響應(yīng)擾動值為10,靜態(tài)放大系數(shù)為階躍響應(yīng)曲線的穩(wěn)態(tài)值==10之比，所以中水箱傳遞函數(shù)為。xi=0:3:1500。)在MATLAB中繪出曲線如下： 下水箱擬合曲線 下水箱模型計算曲線同上，斜率K為P(t)導(dǎo)數(shù)在t=，以此做切線交穩(wěn)態(tài)值于A點,A點映射在t軸上的B點的值為T。過程建模對于實現(xiàn)生產(chǎn)過程的自動化具有十分重要的意義。PID控制器問世至今已有近70年歷史，它以其結(jié)構(gòu)簡單、穩(wěn)定性好、工作可靠、調(diào)整方便而成為工業(yè)控制的主要技術(shù)之一。PID控制器就是根據(jù)系統(tǒng)的誤差，利用比例、積分、微分計算出控制量進行控制的。其控制器的輸出與輸入誤差信號成比例關(guān)系。為了消除穩(wěn)態(tài)誤差，在控制器中必須引入“積分項”。 微分（D）控制在微分控制中，控制器的輸出與輸入誤差信號的微分（即誤差的變化率）成正比關(guān)系。這就是說，在控制器中僅引入 “比例”項往往是不夠的，比例項的作用僅是放大誤差的幅值，而目前需要增加的是“微分項”，它能預(yù)測誤差變化的趨勢，這樣，具有比例+微分的控制器，就能夠提前使抑制誤差的控制作用等于零，甚至為負(fù)值，從而避免了被控量的嚴(yán)重超調(diào)。它主要是依據(jù)系統(tǒng)的數(shù)學(xué)模型，經(jīng)過理論計算確定控制器參數(shù)。PID控制器參數(shù)的工程整定方法，主要有臨界比例法、反應(yīng)曲線法和衰減曲線法。 階躍響應(yīng)性能 在完成了被控對象的數(shù)學(xué)模型的建立以及控制系統(tǒng)方案的選擇后，可以在Simulink中對控制方案進行仿真實驗，以驗證方案的可行性和和加深對于PID參數(shù)調(diào)整的定性認(rèn)識。 SIMULINK仿真框圖 加入副回路的仿真 在時間為0時對系統(tǒng)加入大小為30的階躍信號，設(shè)置主控制器PID參數(shù)KP=6， TI=，TD=120。 SIMULINK加入擾動仿真框圖 MATLAB加入副回路擾動仿真曲線 MATLAB不加入副回路擾動仿真曲線，引入副回路組成三容水箱液位串級控制系統(tǒng)后能夠很好的克服進入副回路的擾動,。 20世紀(jì)50年代前后，一些工廠企業(yè)的生產(chǎn)過程實現(xiàn)了儀表化和局部自動化。本次設(shè)計所要實現(xiàn)的儀表控制系統(tǒng)方案中所使用的調(diào)節(jié)器就是一種智能單元組合儀表。本系統(tǒng)使用的BP800型壓力傳感器廣泛應(yīng)用與石油、化工、冶金、建材等企事業(yè)單位，實現(xiàn)對流體壓力的測量，并適用于各種場合全天候環(huán)境及各種腐蝕性液體。安裝、使用簡便。（2）輸入采用數(shù)字校正系統(tǒng)，內(nèi)置常用熱電偶和熱電阻非線形校正表格，測量精確穩(wěn)定。 儀表控制系統(tǒng)突加階躍信號過渡過程曲線穩(wěn)態(tài)值為5cm,階躍量為1cm.調(diào)節(jié)器1的參數(shù):P=70。D=0調(diào)節(jié)器3的參數(shù):P=10。該上位機控制系統(tǒng)實際上屬于計算機DDC直接數(shù)字控制系統(tǒng)，只不過是將模擬量輸入AI模塊和模擬量輸出AO模塊，開關(guān)量輸入/輸出DI,DO模塊置于計算機之外，計算機由RS232/485通訊轉(zhuǎn)換裝置同ICP7000系列模塊（自帶RS485通訊接口）通訊。在這次設(shè)計中所使用的組態(tài)軟件是北京昆侖通態(tài)出品的MCGS組態(tài)軟件，這是一款優(yōu)秀的國產(chǎn)全中文工控組態(tài)軟件。MCGS具有操作簡便、可視性好、可維護性強、高性能、高可靠性等突出特點，已成功應(yīng)用于石油化工、鋼鐵行業(yè)、電力系統(tǒng)、水處理、環(huán)境監(jiān)測、機械制造、交通運輸、能源原材料、農(nóng)業(yè)自動化、航空航天等領(lǐng)域，經(jīng)過各種現(xiàn)場的長期實際運行，系統(tǒng)穩(wěn)定可靠。支持目前絕大多數(shù)硬件設(shè)備，同時可以方便地定制各種設(shè)備驅(qū)動；此外，獨特的組態(tài)環(huán)境調(diào)試功能與靈活的設(shè)備操作命令相結(jié)合，使硬件設(shè)備與軟件系統(tǒng)間的配合天衣無縫。完善的安全機制，允許用戶自由設(shè)定菜單、按鈕及退出系統(tǒng)的操作權(quán)限。提供了WWW瀏覽功能，能夠方便地實現(xiàn)生產(chǎn)現(xiàn)場控制與企業(yè)管理的集成。D=25調(diào)節(jié)器2的參數(shù):P=30。D=0調(diào)節(jié)器1的設(shè)定值為7cm,突加階躍后設(shè)定值到8cm,此時超調(diào)量為25%，調(diào)整時間為8分鐘（2%誤差帶），穩(wěn)態(tài)誤差0。2）儀表控制系統(tǒng)，控制規(guī)律由硬件實現(xiàn)，要修改控制規(guī)律，必須要改變硬件結(jié)構(gòu)，如AI智能調(diào)節(jié)儀。6結(jié)論 液位是工業(yè)生產(chǎn)過程中重要的被控量之一，因而液位控制的研究具有很大的現(xiàn)實意義。水箱數(shù)學(xué)模型的建立是設(shè)計的開始和關(guān)鍵，通過采集的數(shù)據(jù)在MATLAB上通過數(shù)據(jù)擬合得到各水箱階躍曲線，然后通過曲線可得到各水箱的一階傳遞函數(shù)中的參數(shù)K和T,進而可得到三容水箱的傳遞函數(shù)。如果沒有老師幫助我解決在設(shè)計過程中困惑，我也很難順利完成這次畢業(yè)設(shè)計。設(shè)計很多關(guān)鍵的地方我都是靠和同學(xué)的請教和討論才能順利完成，因此，同學(xué)的幫助也是我完成畢業(yè)設(shè)計的一個重要支撐。 that could also be represented in third party cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (NonRecurring Engineering) and recurring ponent cost.By the late 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could pile HDL descriptions into a gatelevel netlist. This enabled a style of design called standardcell design. Standardcell Integrated Circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice.These steps, implemented with a level of skill mon in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.A team of design engineers starts with a nonformal understanding of the required functions for a new ASIC, usually derived from requirements analysis.*The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a puter program in a highlevel language. This is usually called the RTL (register tra。附錄：英文資料及譯文1. 英文資料 The Integrated Circuit Digital logic and electronic circuits derive their functionality from electronic switches called transistor. Roughly speaking, the transistor can be likened to an electronically controlled valve whereby energy applied to one connection of the valve enables energy to flow between two other bining multiple transistors, digital logic building blocks such as AND gates and flipflops are formed. Transistors, in turn, are made from semiconductors. Consult a periodic table of elements in a college chemistry textbook, and you will locate semiconductors as a group of elements separating the metals and are called semiconductors because of their ability to behave as both metals and nonmetals. A semiconductor can be made to conduct electricity like a metal or to insulate as a nonmetal does. These differing electrical properties can be accurately controlled by mixing the semiconductor with small amounts of other elements. This mixing is called doping. A semiconductor can be doped to contain more electrons (Ntype) or fewer electrons (Ptype). Examples of monly used semiconductors are silicon and germanium. Phosphorous and boron are two elements that are used to dope Ntype and Ptype silicon, respectively. A transistor is constructed by creating a sandwich of differently doped semiconductor layers. The two most mon types of transistors, the bipolarjunction transistor (BJT) and the fieldeffect transistor (FET) are schematically illustrated in Figure figure shows both the silicon structures of these elements and their graphical symbolic representation as would be seen in a circuit diagram. The BJT shown is an NPN transistor, because it is posed of a sandwich of NPN doped silicon. When a small current is injected into the base terminal, a larger current is enabled to flow from the collector to the FET shown is an Nchannel FET, which is posed of two Ntype regions separat