外文翻譯---基于dds參數(shù)可調(diào)諧波信號發(fā)生器的研究(文件)
【正文】 lly converted by the amplitude convertor. When the second highest bit is 1, the Lbit address should be symmetrically converted by the address convertor. 4. System design based on FPGA The system can be divided into two function modules: sine wave generation module and harmonic synthesis module. Sine wave generation module is the key part of the system. It can be divided into phase accumulator module and ROM pression module . Altera FPGA EP2C5Q208C8 is adopted as the core ponent of the system. VHDL is used to program the whole system. Compilation and simulation are implemented in Quartus Ⅱ . . Sine wave generation module phase accumulator module is posed of 24bit accumulator and 11bit adder. Under the control of system clock, the output of 24bit accumulator is accumulated with 9bit frequency control word. Then 11bit adder adds 11bit phase control word to the output of accumulator. High 13bit of the final result are used as address to query the ROM pression module. ROM pression module is posed of address convertor, amplitude convertor and ROM table. 13bit address of phase accumulator module is divided into three parts. The highest bit is used as trigger signal of the amplitude convertor. The second highest bit is used as trigger signal of the address convertor. The low 11bit are used to query the ROM table. Then sampled amplitudes of sine wave are generated. Simulation result of sine wave generation module is shown in . Frequency control word is set as 50 while phase control word is set as 180. When the enable signal is turned into low level, the first output value is the waveform data of address 180 in the ROM table. With each rising edge of system clock, the waveform data of address 180, 181, 182, 183 are sent out. The output values are respectively 76, 76, 77, 77. . Harmonic synthesis module Harmonic synthesis module implements the synthesis of fundamental wave, 3th harmonic, 5th harmonic and 7th harmonic. The 3th, 5th and 7th harmonic data are respectively multiplied by their proportion control words. Then the results of multiplication are added to the fundamental wave data. The realization of multiplication is the emphasis of the module. Because it is difficult to implement the multiplication of floatingpoint format on FPGA, harmonic proportion is divided into numerator and denominator. The numerator is defined as proportion control word while the denominator is 100. Firstly, harmonic data is multiplied by the proportion control word in the multiplier. Then, the product of multiplier is divided by 100 in the divider. Finally, the remainder is excluded and the quotient is preserved. Using Altera IP tools, the multiplier and the divider of harmonic synthesis module are realized. Block diagram of harmonic synthesis module is shown. Simulation result of harmonic synthesis module is. Control words are
畢業(yè)設(shè)計相關(guān)推薦
鄂ICP備17016276號-1