【正文】 68HC11, and also es from Microchip’s PIC family, a more modern design that’s expanded rapidly in the past few years. Atmel hopes AVR will appeal to embedded designers who are willing to tackle a new architecture to get more performance than the entrenched microcontroller families can provide. AVR is the first inhouse CPU design from Atmel, a billiondollar pany better known for its flash memory and E2PROM products. The pany also sells a dozen flashbased derivatives of the popular 8051family, which it produces under license from Intel. Design Melds RISC and Microcontroller Ideas The CPU resembles most RISC processors but has smaller registers. It was originally developed by a pair of researchers in Trondheim,Norway, before their consultancy was acquired by Atmel in 1995. Core CPU development still takes place in Norway, while memory and peripheral development is centered in Atmel’s San Jose (Calif.) facility. The core features 32 identical 8bit registers, as Figure 1 shows. Any register can hold addresses or data. Since 8bit address pointers are fairly worthless even in an 8bit device, the last six registers can be used in pairs, as address pointers. Dubbed X, Y, and Z, these three metaregisters can be used for any load or store operation. The pointers can be post incremented or predecremented at the programmer’s option. Finally, a 6bit displacement can be added to the contents of the pointer, a useful option for addressing array elements. This mode is not available for the X pointer。 even Motorola’s newer 68HC12 (see MPR 5/27/96, p. 1) needs 3 clocks. Atmel expects to deploy its multiplier in future AVR chips as clock speeds increase and the chips take on simple signalprocessing tasks. Instructions Are Rich in Bit Manipulation As with most microcontrollers, the AVR family has a host of bittwiddling options, including 16 explicit instructions to set and clear every flag in its status register. This seems like a lopsided use of op code space。 only in a 40pin package do the chips bond out their address and data buses for access to external memory. All the parts are fabricated on Atmel’s four twolayermetal fab lines in Colorado Springs and Rousset (France). This is the same memory process Atmel uses for its E2PROM and flash devices, and for its 8051 chips with integrated flash. The 1200 measure about 24mm2 overall, and as the die photo in Figure 2 shows, the chip is nearly all logic. Memory processes typically don’t produce very pact (or fast) logic, but most AVR chips will be dominated by memory and peripherals, and clock speeds aren’t very high. Figure 2. The 90S1200 measures about 180。 Philips and Intel are enticing 8051 users with the 8051XA (see MPR 10/3/94, p. 17) or the 251 family. Of these, Intel offers the smoothest upgrade path, with plete binary patibility between the 8051 and the 251. Philips and Motorola both tout substantial size and speed advantages for users willing to reassemble (or repile) their code. The ’HC12, 8051XA, and 251 are more accurately 16 bit designs, with 16bit internal data paths and 16bit arithmetic operations, but they still require three or more clocks for