【正文】 1 基于 FPGA 數(shù)字頻率計(jì)的設(shè)計(jì)和實(shí)現(xiàn) 摘 要 近些年來(lái)，隨著微電子技術(shù)的發(fā)展，可編程邏輯器件在集成度、速度等性能方面也獲得了空前的發(fā)展，數(shù)字頻率計(jì)是數(shù)字信號(hào)處理中的重要內(nèi)容之一，本文主要研究了如何使用 FPGA設(shè)計(jì)和實(shí)現(xiàn)數(shù)字頻率計(jì)，詳細(xì)論述了利用 VHDL 硬件描述語(yǔ)言設(shè)計(jì) ,并在 EDA(電子設(shè)計(jì)自動(dòng)化 ) 工具的幫助下 ,用大規(guī)模可編程邏輯器件 (FPGA/ CPLD) 實(shí)現(xiàn)數(shù)字頻率計(jì)的設(shè)計(jì)原理及相關(guān)程序。特點(diǎn)是 :無(wú)論底層還是頂層文件均用VHDL 語(yǔ)言編寫(xiě) ,避免了用電路圖形式設(shè)計(jì)時(shí)所引起的毛刺現(xiàn)象 。改變了以往數(shù)字電路 小規(guī)模多器件組合的設(shè)計(jì)方法 ,整個(gè)頻率計(jì)設(shè)計(jì)在一塊 FPGA/ CPLD 芯片上 ,與用其他方法做成的頻率計(jì)相比 ,體積更小 ,性能更可靠。 關(guān)鍵字 ： 數(shù)字頻率計(jì) 。電子設(shè)計(jì)自動(dòng)化 。大規(guī)?？删幊踢壿嬈? 2 Abstract With the development of the microelectronic technology, much improvement has been achieved in the PLD techniques. Digital cymometer is one of the important contents of digital signal process. This paper has studied how to design and realize digital cymometer with FPGA ， discusses digital cymometer design principles and procedures by using VHDL hardware descriptive programming ,EDA tools and on the basis of grand scale programmable logic device FPGA/ CPLD. The main point of this article is that bothbottom’ s and top’ s documents are written by VHDL programming , which avoids“ rough phenomenon” , a phenomenon caused by using electric circuit picture style design. This software procedure is different from traditional digital circuit design at small scale and posed of many devices. Instead , the whole cymometer is designed on a FPGA/ CPLD and is posed of a decimal system cymometer. Compared with other cymometer , it is small in volume and has reliable functions. Key words: digital cymometer 。 EDA。 FPGA/ CPLD 3 目錄 摘 要 ........................................................................................................................... 1 Abstract ........................................................................................................................ 2 目錄 ............................................................................................................................. 3 第 1章 緒 論 ........................................................................................................... 4 引言 ............................................................................................................... 4 數(shù)字頻率計(jì)的工作原理 ................................................................................... 5 FPGA實(shí)現(xiàn)頻率計(jì)的優(yōu)點(diǎn) .................................................................................. 6 本文研究?jī)?nèi)容 ................................................................................................. 6 第 2章 MAX+PLUS II軟件介紹 ..................................................................................... 8 MAX+plus II簡(jiǎn)介 .......................................................................................... 8 AX+plus II的主要特點(diǎn) .................................................................................. 8 設(shè)計(jì)流程 ........................................................................................................ 9 第 3章 數(shù)字頻率計(jì)的 FPGA設(shè)計(jì) ............................................................................... 11 FPGA的結(jié)構(gòu)與編程原理 ............................................................................ 11 Xilinx FPGA的結(jié)構(gòu)與編程原理 ......................................................... 11 Xilinx FPGA設(shè)計(jì)流程及本文的設(shè)計(jì)方式選擇 .................................... 13 FPGA設(shè)計(jì)原則 ................................................................................... 14 ........................................................................................ 15 數(shù)字頻率計(jì)的測(cè)量方案選取 ............................................................... 15 測(cè)量方案確定 .................................................................................... 16 第 4章 簡(jiǎn)易數(shù)字頻率計(jì)的設(shè)計(jì) ................................................................................. 18 數(shù)字頻率計(jì)的軟件實(shí)現(xiàn) ................................................................................. 18 頻率計(jì)的整體實(shí)現(xiàn)結(jié)構(gòu) ...................................................................... 18 頻率計(jì)的具體設(shè)計(jì) ............................................................................. 19 數(shù)字頻率計(jì)的硬件實(shí)現(xiàn) ............................................................................. 23 硬件開(kāi)發(fā)系統(tǒng)簡(jiǎn)介 ............................................................................. 23 芯片介紹 ............................................................................................. 23 具體實(shí)現(xiàn) ............................................................................................. 24 第 5章 數(shù)字頻率計(jì)功能的擴(kuò)展 .................................................................................. 25 框圖及信號(hào)流程 ........................................................................................... 25 比較限幅整形電路 ........................................................................................ 25 功能選擇電路 ............................................................................................... 26 閘門(mén)電路 ...................................................................................................... 27 時(shí)基發(fā)生器與控制電路 ................................................................................. 27 計(jì)數(shù)與譯碼電路 ........................................................................................... 28 第 6章 結(jié)束語(yǔ) ....................................................................................................... 30 ............................................................................................................. 30 感謝 ............................................................................................................. 30 參 考 文 獻(xiàn) .............................................................................................................. 31 附圖一 可編程控制芯片時(shí)序仿真圖 .................................................................... 32 附錄 .........................