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Monte Carlo simulation ……for better yield and performance A tutorial start System requirement Statistical analysis include process, mismatch effects Initial design Design meets the goal ? end NO YES Monte Carlo simulation ……for better yield and performance ? Some design may degrade in performance ?Overall design yield could be unexpectedly low If fabrication process parameter and device mismatch effect on same die are not taken in to account then? Hence statistical analysis must find a high place in design cycle ?We will perform Monte Carlo analysis on an RFfront end LNA and pare the result if no statistical analysis is done. ?We will also see how to analyze yield and scalar data in Monte Carlo with the help of Low pass filter example. Monte Carlo simulation Monte Carlo simulation(example) Linearity Input matching Bias N/W Output matching Cascode reduce feedback capacitance RFfront end (LNA) ? Knowing System requirement ? Initial design based on requirement like noise,gain,narrow or wide band. Monte Carlo simulation Cadence simulation setup (Normal) 1. Choosing affirma analog artist 2. Choosing Spectre simulator Choosing model file,which contains all MOS,reg.,cap model parameters. Monte Carlo simulation setup? model libraries and choose model file in the directory Cadence simulation setup (Normal) Set up analysis(dc,ac,sp etc.),create list and run simulator Monte Carlo simulation analysis to run output to plot list and run Cadence simulation setup (Normal) Plotting results Monte Carlo simulation direct plot for analysis to view the desired result waveform Cadence simulation setup (Normal) Monte Carlo modeling in Cadence spectre simulator ? Process Section describes manufacturing parameter,their statistical variation and a model for device that calculates its(width,length,cap,res. Etc.)according to process parameter. ?Design Specific Section – designer according to his need can specify Monte Carlo example in a current mirror circuit,matched transistors are used and designer can give some correlation factor between these matched transistor. Monte Carlo simulation Cadence simulation setup (Monte Carlo) Typical Model File Process Section 1. All parameter sets to their nominal value ,no statistical variation defined 2. Model (NMOS’s Rg) is calculated using nominal parameter value 2 1 Monte Carlo simulation Cadence simulation setup (Monte Carlo) Defining process,mismatch parameter as statistically assigned value Assesses the device mismatch on different die, which could have gone through some different process parameters during fabrication. Assesses the device mismatch on same die,which could have gone through some different process parameter. Variation defined as a distributed function Monte Carlo simulation Process Section Cadence simulation setup (Monte Carlo) Design Specific Section This includes the circuit connectivity(two resistors, and corresponding current sources that feed them) Defining correlation between two devices(R1,R2) ? ?Note :Alternatively this information can also be inserted through Artist Monte Carlo Tool.